Machine type: Shared-memory multi-vectorprocessor.
Operating system: SUPER-UX (NECs Unix variant).
Compilers: Fortran 77, Fortran 90, HPF, C, C++.
|Theor. peak performance:|
|64-bit precision||1 Tflop/s|
|Main memory||128 GB|
|Extended memory||384 GB|
|Communication bandwidth||128 GB/s|
|No. of processors||1-512|
Note: The and values as given above stem from a 32 processor SX-4.
The SX-4 series is the third generation of NECs supercomputers, the first being the SX-2. The architecture is in many respect different from its predecessors although the basic processor resembles the structure of the earlier SX-3 machine. However, the basic processor is implemented in the cheaper CMOS technology instead of ECL which makes them much smaller and cheaper and can be air-cooled. The basic processor in this system will be a 2 Gflop/s vector processor of which up to 32 can be placed in what is called (confusingly) a ``node''. Up to 16 nodes can be connected to a system of 512 processors maximum with a theoretical peak performance of 1 Tflop/s by an Internode Crossbar Switch (IXS) or HIPPI switch. The maximal model should attain a bisectional bandwidth of 128 GB/s for the IXS switch. The SX-4 shows a similar structure as described for the SPP1200 and the Silicon Graphics Power Challenge Array: A multiple CPU shared-memory architecture within a node and a message passing distributed programming model between nodes. For the message passing MPI will be employed.
Furthermore, Fortran 77, Fortran 90, HPF, and C will be provided with a C++ precompiler in addition. Also profiling and performance analysing tools, ANALYZER/SX and PARALLELIZER/SX will be available.
The range of models that are offered is large: 4 ``compact'' models with up to four processors are available. Furthermore, within a single-node model 4, 8, 16, and 32 processor are possible. Of the multi-node systems models with 2, 4, 8, and 16 nodes are offered.