Workshop on Batched, Reproducible, and Reduced Precision BLAS

 

February 23-25, 2017

 

http://bit.ly/Batch-BLAS-2017

last updated: 2/26/17 5:58 PM

 

 

This workshop will touch on extending the Basic Linear Algebra Software Library (BLAS). The existing BLAS have proven to be very effective in assisting portable, efficient software for sequential and some of the current class of high-performance computers. We would like to investigate the possibility of extending the currently accepted standards to provide greater parallelism for small size operations, reproducibility, and reduced precision support. This is the second workshop of an open forum to discuss and formalize details related to batched, reproducible, and reduced precision BLAS. The agenda and the talks from the first workshop can be found here: http://bit.ly/Batch-BLAS-2016

 

The purpose of the workshop is to consider defining a standard interface for the Batched BLAS, Reproducible BLAS, and Reduced Precision BLAS. While these are separate issues we will have presentations and discussions on the need and issues related to these topics.

 

Workshop Format:

We will start the workshop at 9:00 am on Friday, February 24th and plan to finish around 4:00 pm on Saturday, February 25th. The structure will be for the vendors to describe what they have in terms of hardware and mathematical software for their HPC systems, various reports from hardware and software vendors and developers on what they need in terms of numerical linear algebra software for today’s and future systems. The authors of the Batched, Reproducible, and Reduced Precision BLAS will present the current proposal and various implements (reference and more specific ones). We will have discussion on various aspects of the plans.


 

 

Workshop Location:

The workshop will be held in Atlanta on the GATech campus in the Klaus Building room 1116E on February 24th (Friday) and 25th (Saturday) before the SIAM CSE meeting which will be in Atlanta (February 27th-March 3rd).

Directions to Klaus Building:

http://www.cse.gatech.edu/content/maps-directions-0#kacb

 

If you will be staying at the Hilton Atlanta (the SIAM hotel) you can find directions to the GATech campus here:

https://www.dropbox.com/s/6s41ynknlwlg9fq/directions.pdf?dl=0

 

 

From the GATech Hotel walk down 5th St NW. You will see the Klaus Building. Walk up the steps and continue, the entrance is on the right by the green area. Walk into the building and 1116E is on this floor on the left.

 

Hotel Information:

If you don’t already have a hotel reservation for the BBLAS Workshop, GATech has allocated a block of rooms at the GATech Hotel for February 23-26, 2017. Here are the details:

 

Click on the link to book your reservations for Workshop on Batched, Reproducible & Reduced Precision BLAS on February 23rd, 2017 through February 26th, 2017.

 

Workshop on Batched, Reproducible & Reduced Precision BLAS-Reservations Link

 

 

Guests can also access the Workshop on Batched, Reproducible & Reduced Precision BLAS link by logging on to our website www.gatechhotel.com, clicking on the “Group Booking Code” at the top of the page and entering the group password – “wbrrp17”) lower-case letters only.

Hotel reservations hours are Monday through Friday 8am-5:30pm; Saturday 9am-3pm.

 

Booking Deadline: 02/01/2017

For any additional nights needed before or after the posted group dates, please contact the hotel directly at (800)706-2899 to check availability.

 

For those attendees driving to the hotel, overnight parking is $15 per night.

(For unlimited in and out access to the garage, an $18 pass is available.)

 

Atlanta's mass transit, MARTA, has $1 extra fee for paper tickets. People staying for SIAM CSE or other purposes may find the http://www.itsmarta.com/how-to-guide.aspx $2 reload-able MARTA Breeze Card to be a better value.  The cards should be available at the airport MARTA station from a vending machine. The Breeze Card changed last year, so older ones may not function. Ride-sharing services like Uber and Lyft also operate in Atlanta and can pick up at the airport.

Here’s a link to MARTA http://www.itsmarta.com/where-to-buy.aspx

 

Workshop Sponsors in Part by:

 

 

 

 

 

 

 

 

 


Draft Agenda:

Thursday

February 23rd

6:00 PM -8:00 PM

Reception; Georgia Tech Hotel; Conference Room E; 800 Spring St NW, Atlanta, GA;  Sponsored by Intel

Friday

February 24th

Klaus Building

Room 1116E

8:00 AM

Breakfast available

 

9:00 AM

Welcome& Introduction of Participants

Jack Dongarra, UTK

9:30

Report on the first Workshop, May 2016 in Knoxville, TN

Sven Hammarling, U of Manchester

10:00

Standardizing the Batched BLAS API and Memory Layout

Sam Relton, U of Manchester

10:30

Autotuning

Jakub Kurzak and Piotr Luszczek, UTK

11:00

Break

Room

11:30

A proposed modification to the batch BLAS interface

Ahmad Ahmad, UTK

12:00

Reproducible BLAS & Discussion & Update on the XBLAS

Jim Demmel, UCB & Greg Henry, Intel

1:00

Lunch provided

Room

1:30

MAGMA Batched Computations: Approaches and Applications

Stan Tomov, UTK

2:00

High Performance Design of Batched Tensor Computations: Performance Analysis, Modeling, Tuning and Optimization

Azzam Haidar, UTK

2:30

Half Precision Benchmarks

Piotr Luszczek, UTK

3:00

KokkosKernels: Compact Layouts for Batched Blas and Sparse Matrix-Matrix multiply

Siva Rajamanickam, SNL

3:30

Break

Room

4:00

Status of the NLAFET Project

Bo Kagstrom, Umea U

4:30

Integer GEMM

Murat Gurney, Intel

7:00

Dinner Alma Cocina; 191 Peachtree Street NE, Atlanta

Sponsored by Intel


 

Saturday

February 25th

Klaus Building

Room 1116E

8:00 AM

Breakfast available

 

9:00 AM

The Landscape of High-Performance Tensor Contractions

Paul Springer, Aachen

9:30

Batched Factorization and Inversion Routines for Block-Jacobi Preconditioning on GPUs

Hartwig Anzt, UTK

10:00

Exploiting Batched Operation in Applications

David Keyes and Hatem Ltaief, KAUST

10:30

Auto-tuning Work for the QR Factorization Kernel

Wissam Lakhdar, Texas A&M

11:00

Break

Room

Vendor presentations

11:30

Intel, Compact Batched BLAS

Tim Costa, Intel

12:00

ARM

Chris Goodyer, ARM

12:30

Lunch provided

Room

Vendor presentations continued

1:30

NAG

Mike Dewar, NAG

2:00

MathWorks

Pat Quillen, MathWorks

2:30

Nvidia

Chris Cecka, Nvidia

3:00

Adobe

Shoaib Kamil, Adobe

3:30

Wrap up

Jack Dongarra

 


group-pict2.jpg

 

 

Draft Reports:

You can find a draft copy of the Batched BLAS and Reproducible

 

Batched BLAS Draft Reports:

https://www.dropbox.com/s/olocmipyxfvcaui/batched_api_03_30_2016.pdf?dl=0

 

Comparison of Batched BLAS Interfaces:

http://www.nlafet.eu/wp-content/uploads/2016/01/NLAFET-WN5-Relton-ValeroLara-Zounon-161111.pdf

 

Batched BLAS Poster:

https://www.dropbox.com/s/ddkym76fapddf5c/Batched%20BLAS%20Poster%2012.pdf?dl=0

 

Batched BLAS Slides:

https://www.dropbox.com/s/kz4fhcipz3e56ju/BatchedBLAS-1.pptx?dl=0

 

Webpage on ReproBLAS:

http://bebop.cs.berkeley.edu/reproblas/

 

Efficient Reproducible Floating Point Summation and BLAS:

http://www.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-229.pdf

 

A Proposal for a Next-Generation BLAS

Contributors: J. Demmel, G. Henry, X.S. Li, J. Riedy, P.T.P. Tang

https://docs.google.com/document/d/1DY4ImZT1coqri2382GusXgBTTTVdBDvtD5I14QHp9OE/edit

 

API the Compact Batched BLAS, Intel MKL Team 

https://www.dropbox.com/s/gplop3sxhg8le3r/MKL_COMPACT_v4.docx?dl=0

 

If you have any questions please let me know (dongarra@icl.utk.edu).

 


 

Attendees:

Ahmad

Ahmad

UTK

aahmad2@icl.utk.edu

Hartwig

Anzt

UTK

hanzt@icl.utk.edu

Konstantin

Arturov

Intel

konstantin.i.arturov@intel.com

Mohsen

Aznaveh

Texas A&M

mahmoudi.mohsen@gmail.com

Cris

Cecka

Nvidia

ccecka@nvidia.com

Edmomd

Chow

GATech

echow@cc.gatech.edu

Tim

Costa

Intel

timothy.b.costa@intel.com

Jim

Demmel

UCB

demmel@EECS.Berkeley.EDU

Mike

Dewar

NAG

mike.dewar@nag.co.uk

Jack

Dongarra

UTK

dongarra@icl.utk.edu

Iain

Duff

Rutherford

iain.duff@stfc.ac.uk

Marat

Dukhan

GATech

mdukhan3@gatech.edu

Mark

Gates

UTK

mgates3@utk.edu

Chris

Goodyer

ARM

Chris.Goodyer@arm.com

Laura

Grigori

INRIA

laura.grigori@inria.fr

Murat

Guney

Intel

murat.e.guney@intel.com

Azzam

Haidar

UTK

haidar@icl.utk.edu

Sven

Hammarling

Manchester

sven.hammarling@btinternet.com

Greg

Henry

Intel

greg.henry@intel.com

Nick

Higham

Manchester

higham@maths.manchester.ac.uk

David

Hough

UCB

lapack@ucbtest.org

Jinbin

Ju

Texas A&M

jinbinju@tamu.edu

Bo

Kagstrom

Umea

bokg@cs.umu.se

Shoaib

Kamil

Adobe

kamil@adobe.com

David

Keyes

KAUST

david.keyes@kaust.edu.sa

Sarah

Knepper

Intel

sarah.knepper@intel.com

Jakub

Kurzak

UTK

kurzak@icl.utk.edu

Jiajia

Li

GATech

jiajiali@gatech.edu

Florent

Lopez

Rutherford

florent.lopez@stfc.ac.uk

Hatem

Ltaief

KAUST

hatem.ltaief@kaust.edu.sa

Piotr

Luszczek

UTK

luszczek@icl.utk.edu

Carl Christian Kjelgaard

Mikkelsen

Umea

spock@cs.umu.se

Mirko

Myllykoski

Umea

mirkom@cs.umu.se

Pat

Quillen

MathWorks

Pat.Quillen@mathworks.com

Siva

Rajamanickam

SNL

srajama@sandia.gov

Sam

Relton

Manchester

samuel.relton@manchester.ac.uk

Jason

Riedy

GATech

jason.riedy@cc.gatech.edu

Wissam

Sid-Lakhdar

Texas A&M

 wissam@tamu.edu

Paul

Springer

Aachen

paul.springer@rwth-aachen.de

Shane

Story

Intel

shane.story@intel.com

Stan

Tomov

UTK

tomov@icl.utk.edu

Rich

Vuduc

GATech

richie@cc.gatech.edu

Stephen

Wood

UTK

swood@icl.utk.edu

Ichi

Yamazaki

UTK

iyamazak@utk.edu

Mawussi

Zounon

Manchester

mawussi.zounon@gmail.com