%%% -*-BibTeX-*-
%%% ====================================================================
%%%  BibTeX-file{
%%%     author          = "Nelson H. F. Beebe",
%%%     version         = "1.27",
%%%     date            = "05 May 2014",
%%%     time            = "14:56:24 MDT",
%%%     filename        = "jetc.bib",
%%%     address         = "University of Utah
%%%                        Department of Mathematics, 110 LCB
%%%                        155 S 1400 E RM 233
%%%                        Salt Lake City, UT 84112-0090
%%%                        USA",
%%%     telephone       = "+1 801 581 5254",
%%%     FAX             = "+1 801 581 4148",
%%%     URL             = "http://www.math.utah.edu/~beebe",
%%%     checksum        = "24265 8684 45591 444633",
%%%     email           = "beebe at math.utah.edu, beebe at acm.org,
%%%                        beebe at computer.org (Internet)",
%%%     codetable       = "ISO/ASCII",
%%%     keywords        = "ACM Journal on Emerging Technologies in
%%%                        Computing Systems (JETC); bibliography;
%%%                        BibTeX",
%%%     license         = "public domain",
%%%     supported       = "no",
%%%     docstring       = "This is a COMPLETE BibTeX bibliography for
%%%                        the journal ACM Journal on Emerging
%%%                        Technologies in Computing Systems (JETC)
%%%                        (CODEN unknown, ISSN: 1550-4832 (print),
%%%                        1550-4840 (electronic)), for 2005--date.
%%%
%%%                        Publication began with volume 1, number 1,
%%%                        in March 2005.  The journal appears
%%%                        quarterly.
%%%
%%%                        The journal has a World-Wide Web site at:
%%%
%%%                            http://www.acm.org/pubs/jetc
%%%
%%%                        Tables-of-contents of all issues are
%%%                        available at:
%%%
%%%                            http://www.acm.org/pubs/contents/journals/jetc/
%%%                            http://portal.acm.org/browse_dl.cfm?idx=J967
%%%
%%%                        Qualified subscribers can retrieve the full
%%%                        text of recent articles in PDF form.
%%%
%%%                        At version 1.27, the COMPLETE journal
%%%                        coverage looked like this:
%%%
%%%                             2005 (   7)    2009 (  19)    2013 (  30)
%%%                             2006 (  11)    2010 (  15)    2014 (  26)
%%%                             2007 (  15)    2011 (  20)
%%%                             2008 (  24)    2012 (  34)
%%%
%%%                             Article:        201
%%%
%%%                             Total entries:  201
%%%
%%%                        Data for this bibliography was derived from
%%%                        data at the ACM Web site.
%%%
%%%                        ACM copyrights explicitly permit abstracting
%%%                        with credit, so article abstracts, keywords,
%%%                        and subject classifications have been
%%%                        included in this bibliography wherever
%%%                        available.
%%%
%%%                        The bibsource keys in the bibliography
%%%                        entries below indicate the data sources.
%%%
%%%                        URL keys in the bibliography point to
%%%                        World Wide Web locations of additional
%%%                        information about the entry.
%%%
%%%                        Spelling has been verified with the UNIX
%%%                        spell and GNU ispell programs using the
%%%                        exception dictionary stored in the
%%%                        companion file with extension .sok.
%%%
%%%                        BibTeX citation tags are uniformly chosen
%%%                        as name:year:abbrev, where name is the
%%%                        family name of the first author or editor,
%%%                        year is a 4-digit number, and abbrev is a
%%%                        3-letter condensation of important title
%%%                        words. Citation tags were automatically
%%%                        generated by software developed for the
%%%                        BibNet Project.
%%%
%%%                        In this bibliography, entries are sorted in
%%%                        publication order, using ``bibsort -byvolume.''
%%%
%%%                        The checksum field above contains a CRC-16
%%%                        checksum as the first value, followed by the
%%%                        equivalent of the standard UNIX wc (word
%%%                        count) utility output of lines, words, and
%%%                        characters.  This is produced by Robert
%%%                        Solovay's checksum utility.",
%%%  }
%%% ====================================================================

@Preamble{"\input bibnames.sty"
    # "\ifx \undefined \circled \def \circled #1{(#1)}\fi"
    # "\ifx \undefined \reg \def \reg {\circled{R}}\fi"
}

%%% ====================================================================
%%% Acknowledgement abbreviations:

@String{ack-nhfb = "Nelson H. F. Beebe,
                    University of Utah,
                    Department of Mathematics, 110 LCB,
                    155 S 1400 E RM 233,
                    Salt Lake City, UT 84112-0090, USA,
                    Tel: +1 801 581 5254,
                    FAX: +1 801 581 4148,
                    e-mail: \path|beebe@math.utah.edu|,
                            \path|beebe@acm.org|,
                            \path|beebe@computer.org| (Internet),
                    URL: \path|http://www.math.utah.edu/~beebe/|"}

%%% ====================================================================
%%% Journal abbreviations:

@String{j-JETC                  = "ACM Journal on Emerging Technologies
                                  in Computing Systems (JETC)"}

%%% ====================================================================
%%% Bibliography entries:

@Article{Irwin:2005:E,
  author =       "Mary Jane Irwin and Vijaykrishnan Narayanan",
  title =        "Editorial",
  journal =      j-JETC,
  volume =       "1",
  number =       "1",
  pages =        "1--6",
  month =        apr,
  year =         "2005",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Sep 17 15:29:54 MDT 2005",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Narendra:2005:CDC,
  author =       "Siva G. Narendra",
  title =        "Challenges and design choices in nanoscale {CMOS}",
  journal =      j-JETC,
  volume =       "1",
  number =       "1",
  pages =        "7--49",
  month =        apr,
  year =         "2005",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Sep 17 15:29:54 MDT 2005",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Lim:2005:PPB,
  author =       "Sung Kyu Lim and Ramprasad Ravichandran and Mike
                 Niemier",
  title =        "Partitioning and placement for buildable {QCA}
                 circuits",
  journal =      j-JETC,
  volume =       "1",
  number =       "1",
  pages =        "50--72",
  month =        apr,
  year =         "2005",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Sep 17 15:29:54 MDT 2005",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Gojman:2005:EDS,
  author =       "Benjamin Gojman and Eric Rachlin and John E. Savage",
  title =        "Evaluation of design strategies for stochastically
                 assembled nanoarray memories",
  journal =      j-JETC,
  volume =       "1",
  number =       "2",
  pages =        "73--108",
  year =         "2005",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Sep 17 15:29:54 MDT 2005",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Dehon:2005:NBP,
  author =       "Andr{\'e} Dehon",
  title =        "Nanowire-based programmable architectures",
  journal =      j-JETC,
  volume =       "1",
  number =       "2",
  pages =        "109--162",
  year =         "2005",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Sep 17 15:29:54 MDT 2005",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Huang:2005:TBQ,
  author =       "J. Huang and M. Momenzadeh and L. Schiano and M.
                 Ottavi and F. Lombardi",
  title =        "Tile-based {QCA} design using majority-like logic
                 primitives",
  journal =      j-JETC,
  volume =       "1",
  number =       "3",
  pages =        "163--185",
  month =        oct,
  year =         "2005",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Mar 7 16:16:02 MST 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chakrabarty:2005:DAM,
  author =       "Krishnendu Chakrabarty and Jun Zeng",
  title =        "Design automation for microfluidics-based biochips",
  journal =      j-JETC,
  volume =       "1",
  number =       "3",
  pages =        "186--223",
  month =        oct,
  year =         "2005",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Mar 7 16:16:02 MST 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Patwardhan:2006:NNS,
  author =       "Jaidev P. Patwardhan and Chris Dwyer and Alvin R.
                 Lebeck and Daniel J. Sorin",
  title =        "{NANA}: {A} nano-scale active network architecture",
  journal =      j-JETC,
  volume =       "2",
  number =       "1",
  pages =        "1--30",
  month =        jan,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 28 07:08:02 MDT 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{VanMeter:2006:AIQ,
  author =       "Rodney {Van Meter} and Mark Oskin",
  title =        "Architectural implications of quantum computing
                 technologies",
  journal =      j-JETC,
  volume =       "2",
  number =       "1",
  pages =        "31--63",
  month =        jan,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 28 07:08:02 MDT 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Xie:2006:DSE,
  author =       "Yuan Xie and Gabriel H. Loh and Bryan Black and Kerry
                 Bernstein",
  title =        "Design space exploration for {$3$D} architectures",
  journal =      j-JETC,
  volume =       "2",
  number =       "2",
  pages =        "65--103",
  month =        apr,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 28 07:08:02 MDT 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Su:2006:YER,
  author =       "Fei Su and Krishnendu Chakrabarty",
  title =        "Yield enhancement of reconfigurable
                 microfluidics-based biochips using interstitial
                 redundancy",
  journal =      j-JETC,
  volume =       "2",
  number =       "2",
  pages =        "104--128",
  month =        apr,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 28 07:08:02 MDT 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Savage:2006:RAN,
  author =       "John E. Savage and Eric Rachlin and Andr{\'e} DeHon
                 and Charles M. Lieber and Yue Wu",
  title =        "Radial addressing of nanowires",
  journal =      j-JETC,
  volume =       "2",
  number =       "2",
  pages =        "129--154",
  month =        apr,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 28 07:08:02 MDT 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Massoud:2006:MDC,
  author =       "Yehia Massoud and Arthur Nieuwoudt",
  title =        "Modeling and design challenges and solutions for
                 carbon nanotube-based interconnect in future high
                 performance integrated circuits",
  journal =      j-JETC,
  volume =       "2",
  number =       "3",
  pages =        "155--196",
  month =        jul,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Nov 16 18:25:43 MST 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Tahoori:2006:AID,
  author =       "Mehdi B. Tahoori",
  title =        "Application-independent defect tolerance of
                 reconfigurable nanoarchitectures",
  journal =      j-JETC,
  volume =       "2",
  number =       "3",
  pages =        "197--218",
  month =        jul,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Nov 16 18:25:43 MST 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Datta:2006:ADF,
  author =       "Kushal Datta and Arindam Mukherjee and Arun
                 Ravindran",
  title =        "Automated design flow for diode-based nanofabrics",
  journal =      j-JETC,
  volume =       "2",
  number =       "3",
  pages =        "219--241",
  month =        jul,
  year =         "2006",
  CODEN =        "????",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Nov 16 18:25:43 MST 2006",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Ottavi:2006:HHE,
  author =       "Marco Ottavi and Luca Schiano and Fabrizio Lombardi
                 and Douglas Tougaw",
  title =        "{HDLQ}: {A HDL} environment for {QCA} design",
  journal =      j-JETC,
  volume =       "2",
  number =       "4",
  pages =        "243--261",
  month =        oct,
  year =         "2006",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1216396.1216397",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:17 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Emerging technologies have attracted a substantial
                 interest in overcoming the physical limitations of CMOS
                 as projected at the end of the Technology Roadmap;
                 among these technologies, quantum-dot cellular automata
                 (QCA) relies on different and novel paradigms to
                 implement dense, low power circuits and systems for
                 high-performance computing. As applicable to existing
                 technologies, a hierarchical process can be utilized to
                 facilitate the design of QCA circuits. Tools and
                 methodologies both at system and physical levels are
                 required to support all design phases. This article
                 presents an HDL model to describe QCA ``devices'' (also
                 referred elsewhere in the technical literature as
                 building blocks, i.e., majority voter, inverter, wire,
                 crossover) and facilitate the evaluation of their
                 design. This tool, referred to as HDLQ, allows a
                 designer to verify the logic characteristics of a QCA
                 system, while supporting within a design environment
                 different operational mechanisms (such as fault
                 injection) and the unique features of QCA (such as
                 bidirectionality and timing/clocking partitioning). The
                 applicability of this design environment to various
                 memory circuits for logic and timing verification is
                 presented in detail. Various defective conditions for
                 kinks due to thermodynamic effects and permanent faults
                 due to manufacturing defects are considered for
                 injection.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "CAD; fault injection; HDL; QCA",
}

@Article{Davids:2006:MFD,
  author =       "Daniel Davids and Siddhartha Datta and Arindam
                 Mukherjee and Bharat Joshi and Arun Ravindran",
  title =        "Multiple fault diagnosis in digital microfluidic
                 biochips",
  journal =      j-JETC,
  volume =       "2",
  number =       "4",
  pages =        "262--276",
  month =        oct,
  year =         "2006",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1216396.1216398",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:17 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Microfluidics-based biochips consist of microfluidic
                 arrays on rigid substrates through which, movement of
                 fluids is tightly controlled to facilitate biological
                 reactions. Biochips are soon expected to revolutionize
                 biosensing, clinical diagnostics, and drug discovery.
                 Critical to the deployment of biochips in such diverse
                 areas is the dependability of these systems. Thus,
                 robust testing techniques are required to ensure an
                 adequate level of system dependability. Due to the
                 underlying mixed technology and energy domains, such
                 biochips exhibit unique failure mechanisms and defects.
                 In this article we present a highly effective fault
                 diagnosis strategy that uses a single source and sink
                 to detect and locate multiple faults in a microfluidic
                 array, without flooding the array, a problem that has
                 hampered realistic implementations of all existing
                 strategies. The strategy renders itself well for a
                 built-in self-test that could drastically reduce the
                 operating cost of microfluidic biochips. It can be used
                 during both the manufacturing phase of the biochip, as
                 well as field operation. Furthermore, the algorithm can
                 pinpoint the actual fault, as opposed to merely the
                 faulty regions that are typically identified by
                 strategies proposed in the literature. Also, analytical
                 results suggest that it is an effective strategy that
                 can be used to design highly dependable biochip
                 systems.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "droplet flooding; faults tolerance; Microfluidic
                 biochip; multiple fault; testing",
}

@Article{Prasad:2006:DSA,
  author =       "Aditya K. Prasad and Vivek V. Shende and Igor L.
                 Markov and John P. Hayes and Ketan N. Patel",
  title =        "Data structures and algorithms for simplifying
                 reversible circuits",
  journal =      j-JETC,
  volume =       "2",
  number =       "4",
  pages =        "277--293",
  month =        oct,
  year =         "2006",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1216396.1216399",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:17 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Reversible logic is motivated by low-power design,
                 quantum circuits, and nanotechnology. We develop a
                 compact representation of small reversible circuits to
                 generate and store optimal circuits for all 40,320
                 three-input reversible functions, and millions of
                 four-input circuits. This allows implementing a
                 function optimally in constant time for use in the
                 peephole optimization of larger circuits produced by
                 existing techniques, and guarantees that every
                 three-bit subcircuit is optimal. To generate
                 subcircuits, we use a graph-based data structure and
                 algorithms for circuit restructuring. Finally, we
                 demonstrate a suboptimal circuit for which peephole
                 optimization fails.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "circuit libraries; Circuit simplification; optimal
                 subcircuit",
}

@Article{Zhao:2007:PTM,
  author =       "Wei Zhao and Yu Cao",
  title =        "Predictive technology model for nano-{CMOS} design
                 exploration",
  journal =      j-JETC,
  volume =       "3",
  number =       "1",
  pages =        "1:1--1:??",
  month =        apr,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1229175.1229176",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:25 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "A predictive MOSFET model is critical for early
                 circuit design research. In this work, a new generation
                 of Predictive Technology Model (PTM) is developed,
                 covering emerging physical effects and alternative
                 structures, such as the double-gate device (i.e.,
                 FinFET). Based on physical models and early stage
                 silicon data, PTM of bulk and double-gate devices are
                 successfully generated from 130nm to 32nm technology
                 nodes, with effective channel length down to 13nm. By
                 tuning only ten primary parameters, PTM can be easily
                 customized to cover a wide range of process
                 uncertainties. The accuracy of PTM predictions is
                 comprehensively verified with published silicon data:
                 the error of the current is below 10\\% for both NMOS
                 and PMOS. Furthermore, the new PTM correctly captures
                 process sensitivities in the nanometer regime. PTM is
                 available online at http://www.eas.asu.edu/~ptm.",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "early design exploration; FinFET; predictive modeling;
                 process variations; Technology scaling",
}

@Article{Schulhof:2007:SRC,
  author =       "Gabriel Schulhof and Konrad Walus and Graham A.
                 Jullien",
  title =        "Simulation of random cell displacements in {QCA}",
  journal =      j-JETC,
  volume =       "3",
  number =       "1",
  pages =        "2:1--2:??",
  month =        apr,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1229175.1229177",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:25 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "We analyze the behavior of quantum-dot cellular
                 automata (QCA) building blocks in the presence of
                 random cell displacements. The QCA cells are modeled
                 using the coherence vector description and simulated
                 using QCADesigner. We evaluate various fundamental
                 circuits: the wire, the inverter, the majority gate,
                 and the two-wire crossing approaches: the coplanar
                 crossover and the multilayer crossover. Our results
                 show that different building blocks have different
                 displacement tolerances. The coplanar crossover and
                 inverter perform the weakest. The wire is the most
                 robust. We have found displacement tolerances to be a
                 function of circuit layout and geometry rather than
                 cell size.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "fabrication variances; fault tolerance; QCA;
                 Quantum-dot cellular automata",
}

@Article{Rose:2007:DCM,
  author =       "Garrett S. Rose and Yuxing Yao and James M. Tour and
                 Adam C. Cabe and Nadine Gergel-Hackett and Nabanita
                 Majumdar and John C. Bean and Lloyd R. Harriott and
                 Mircea R. Stan",
  title =        "Designing {CMOS}\slash molecular memories while
                 considering device parameter variations",
  journal =      j-JETC,
  volume =       "3",
  number =       "1",
  pages =        "3:1--3:??",
  month =        apr,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1229175.1229178",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:25 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In recent years, many advances have been made in the
                 development of molecular scale devices. Experimental
                 data shows that these devices have potential for use in
                 both memory and logic. This article describes the
                 challenges faced in building crossbar array-based
                 molecular memory and develops a methodology to optimize
                 molecular scale architectures based on experimental
                 device data taken at room temperature. In particular,
                 issues in reading and writing such as memory using CMOS
                 are discussed, and a solution is introduced for easily
                 reading device conductivity states (typically
                 characterized by very small currents). Additionally, a
                 metric is derived to determine the voltages for writing
                 to the crossbar array. The proposed memory design is
                 also simulated with consideration to device parameter
                 variations. Thus, the results presented here shed light
                 on important design choices to be made at multiple
                 abstraction levels, from devices to architectures.
                 Simulation results, incorporating experimental device
                 data, are presented using Cadence Spectre.",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "CMOS; molecular electronics; nanotechnology",
}

@Article{McKee:2007:ESI,
  author =       "Sally A. McKee",
  title =        "Editorial to special issue on reliable computing",
  journal =      j-JETC,
  volume =       "3",
  number =       "2",
  pages =        "4:1--4:??",
  month =        jul,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1265949.1265950",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:32 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Eshaghian-Wilner:2007:SWN,
  author =       "Mary M. Eshaghian-Wilner and Alex Khitun and Shiva
                 Navab and Kang L. Wang",
  title =        "The spin-wave nanoscale reconfigurable mesh and the
                 labeling problem",
  journal =      j-JETC,
  volume =       "3",
  number =       "2",
  pages =        "5:1--5:??",
  month =        jul,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1265949.1265951",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:32 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this article, we present a nanoscale reconfigurable
                 mesh which is interconnected by ferromagnetic spin-wave
                 buses. In this architecture, unlike the traditional
                 spin-based nano structures which transmit charge, waves
                 are transmitted. As a result, the power consumption of
                 the proposed modules can be low. This reconfigurable
                 mesh, while requiring the same number of switches and
                 buses as the standard reconfigurable mesh, is capable
                 of simultaneously transmitting $N$ waves on each of the
                 spin-wave buses. Because of this highly parallel
                 feature, very fast and fault-tolerant algorithms can be
                 designed. To illustrate the superior performance of the
                 proposed spin-wave reconfigurable mesh, we present
                 three fast labeling algorithms.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "image processing; nanoscale architectures;
                 reconfigurable mesh; Spin waves",
}

@Article{Prodan:2007:DDE,
  author =       "Lucian Prodan and Mihai Udrescu and Oana Boncalo and
                 Mircea Vladutiu",
  title =        "Design for dependability in emerging technologies",
  journal =      j-JETC,
  volume =       "3",
  number =       "2",
  pages =        "6:1--6:??",
  month =        jul,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1265949.1265952",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:32 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "As current microelectronics will reach their physical
                 limits within the foreseeable future, emerging
                 technologies may offer a solution for maintaining the
                 trends to increase computing performance.
                 Biologically-inspired and quantum computing represent
                 two emerging technology vectors for novel computing
                 architectures within nanoelectronics. However,
                 potential benefits will come at the cost of increased
                 device sensitivity to the surrounding environment. This
                 article provides a dependability perspective over these
                 technologies from a designer's standpoint. Maintaining
                 or increasing the dependability of unconventional
                 computational processes is discussed in two different
                 contexts, a bio-inspired computing architecture (the
                 Embryonics project) and a quantum computational
                 architecture (the QUERIST project).",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "bio-inspired computing; bio-inspired digital design;
                 Dependability; Embryonics; emerging technologies;
                 evolvable hardware; fault-tolerance assessment; quantum
                 computing; reliability",
}

@Article{Tyrrell:2007:ED,
  author =       "Andy M. Tyrrell and Andrew J. Greensted",
  title =        "Evolving dependability",
  journal =      j-JETC,
  volume =       "3",
  number =       "2",
  pages =        "7:1--7:??",
  month =        jul,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1265949.1265953",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:32 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Evolvable hardware offers much for the future of
                 complex systems design. Evolutionary techniques not
                 only have the potential for larger solution space
                 coverage, but when implemented on hardware, also allow
                 system designs to adapt to changes in the environment,
                 including failures in system components. This article
                 reviews a number of novel techniques, all based in the
                 field of bio-inspired systems, that provide varying
                 degrees of dependability over and above standard
                 designs. In particular, three different techniques are
                 considered: using FPGAs and ideas from developmental
                 biology to create designs that possess emergent
                 fault-tolerant properties, using FPGAs and continuous
                 evolution to circumvent faults as and when they occur,
                 and, finally, we consider a novel ASIC designed and
                 built with bio-inspired systems in mind.",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "bio-inspired architectures; Evolutionary algorithms;
                 fault tolerance; RISA architecture",
}

@Article{Sekanina:2007:EFR,
  author =       "Luk{\'a}{\v{s}} Sekanina",
  title =        "Evolutionary functional recovery in virtual
                 reconfigurable circuits",
  journal =      j-JETC,
  volume =       "3",
  number =       "2",
  pages =        "8:1--8:??",
  month =        jul,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1265949.1265954",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:32 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "A virtual reconfigurable circuit (VRC) is a
                 domain-specific reconfigurable device developed using
                 an ordinary FPGA in order to easily implement evolvable
                 hardware applications. While a fast partial runtime
                 reconfiguration and application-specific programmable
                 elements represent the main advantages of VRC, the main
                 disadvantage of the VRC is the area consumed. This
                 study describes experiments conducted to estimate how
                 the use of VRC influences the dependability of
                 FPGA-based evolvable systems. It is shown that these
                 systems are not as sensitive to faults as their
                 area-demanding implementations might suggest. An
                 evolutionary algorithm is utilized to design fault
                 tolerant circuits as well as to perform an automatic
                 functional recovery when faults are detected in the
                 configuration memory of the FPGA. All the experiments
                 are performed on models of reconfigurable devices.",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Dependability; evolutionary algorithms; evolvable
                 hardware; FPGA",
}

@Article{Tempesti:2007:SRH,
  author =       "Gianluca Tempesti and Daniel Mange and Pierre-Andre
                 Mudry and Jo{\"e}l Rossier and Andre Stauffer",
  title =        "Self-replicating hardware for reliability: {The
                 Embryonics Project}",
  journal =      j-JETC,
  volume =       "3",
  number =       "2",
  pages =        "9:1--9:??",
  month =        jul,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1265949.1265955",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:32 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The multicellular structure of biological organisms
                 and the interpretation in each of their cells of a
                 chemical program (the DNA string or genome ) is the
                 source of inspiration for the Embryonics (embryonic
                 electronics) project, whose final objective is the
                 design of highly robust integrated circuits, endowed
                 with properties usually associated with the living
                 world: self-repair and self-replication. In this
                 article, we provide an overview of our latest research
                 in the domain of the self-replication of processing
                 elements within a programmable logic substrate, a key
                 prerequisite for achieving system-level fault tolerance
                 in our bio-inspired approach.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Bio-inspired architectures; embryonic electronics;
                 growth; hierarchical fault tolerance; self-repair;
                 self-replication",
}

@Article{Patwardhan:2007:SOD,
  author =       "Jaidev Patwardhan and Chris Dwyer and Alvin R.
                 Lebeck",
  title =        "A self-organizing defect tolerant {SIMD}
                 architecture",
  journal =      j-JETC,
  volume =       "3",
  number =       "2",
  pages =        "10:1--10:??",
  month =        jul,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1265949.1265956",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:32 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The continual decrease in transistor size (through
                 either scaled CMOS or emerging nanotechnologies)
                 promises to usher in an era of tera to peta-scale
                 integration but with increasing defects. Regardless of
                 fabrication methodology (top-down or bottom-up),
                 defect-tolerant architectures are necessary to exploit
                 the full potential of future increased device
                 densities.\par

                 This article explores a defect-tolerant SIMD
                 architecture (SOSA) that self-organizes a large number
                 of limited capability nodes with high defect rates into
                 SIMD processing elements. Simulation results show that
                 SOSA matches or exceeds the performance of conventional
                 systems for moderate to large problems, but with lower
                 power density.",
  acknowledgement = ack-nhfb,
  articleno =    "10",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "bit-serial; data parallel; defect tolerance; DNA;
                 nanocomputing; Self-organizing; SIMD",
}

@Article{Chakrabarty:2007:ESI,
  author =       "Krishnendu Chakrabarty and Sachin Sapatnekar",
  title =        "Editorial to special issue {DAC 2006}",
  journal =      j-JETC,
  volume =       "3",
  number =       "3",
  pages =        "11:1--11:??",
  month =        nov,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1295231.1295232",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:49 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Paul:2007:PBC,
  author =       "Bipul C. Paul and Shinobu Fujita and Masaki Okajima
                 and Thomas Lee",
  title =        "Prospect of ballistic {CNFET} in high performance
                 applications: {Modeling} and analysis",
  journal =      j-JETC,
  volume =       "3",
  number =       "3",
  pages =        "12:1--12:??",
  month =        nov,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1295231.1295233",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:49 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "With the advent of carbon nanotube technology,
                 evaluating circuit and system performance using these
                 devices is becoming extremely important. In this
                 article, we present a quasi-analytical device model for
                 intrinsic ballistic CNFET, which can be used in any
                 conventional circuit simulator like SPICE. This simple
                 quasi-analytical model is effective in a wide variety
                 of CNFET structures as well as for a wide range of
                 operating conditions in the digital circuit application
                 domain. We also provide insight into how the parasitic
                 fringe capacitance in state-of-the-art CNFET geometries
                 impacts the overall performance of CNFET circuits. We
                 show that unless the device width can be significantly
                 reduced, the effective gate capacitance of CNFET will
                 be strongly dominated by the parasitic fringe
                 capacitances, and the superior performance of intrinsic
                 CNFET over silicon MOSFET cannot be achieved in
                 circuit. We further show that unlike conventional
                 MOSFET, nanotube FETs are significantly less sensitive
                 to many process parameter variations due to their
                 inherent device structures and cylindrical gate
                 geometry.",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Ballistic carbon nanotube FET (CNFET); circuit
                 compatible model; circuit performance; parasitic
                 capacitance; process variability",
}

@Article{Yuh:2007:PDT,
  author =       "Ping-Hung Yuh and Chia-Lin Yang and Yao-Wen Chang",
  title =        "Placement of defect-tolerant digital microfluidic
                 biochips using the {$T$}-tree formulation",
  journal =      j-JETC,
  volume =       "3",
  number =       "3",
  pages =        "13:1--13:??",
  month =        nov,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1295231.1295234",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:49 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Droplet-based microfluidic biochips have recently
                 gained much attention and are expected to revolutionize
                 the biological laboratory procedures. As biochips are
                 adopted for the complex procedures in molecular
                 biology, its complexity is expected to increase due to
                 the need of multiple and concurrent assays on a chip.
                 In this article, we formulate the placement problem of
                 digital microfluidic biochips with a tree-based
                 topological representation, called $T$-tree. To the
                 best knowledge of the authors, this is the first work
                 that adopts a topological representation to solve the
                 placement problem of digital microfluidic biochips. We
                 also consider the defect tolerant issue to avoid to use
                 defective cells due to fabrication. Experimental
                 results demonstrate that our approach is more efficient
                 and effective than the previous unified synthesis and
                 placement framework.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "biochip; Microfluidics; placement",
}

@Article{Xu:2007:ADP,
  author =       "Tao Xu and William L. Hwang and Fei Su and Krishnendu
                 Chakrabarty",
  title =        "Automated design of pin-constrained digital
                 microfluidic biochips under droplet-interference
                 constraints",
  journal =      j-JETC,
  volume =       "3",
  number =       "3",
  pages =        "14:1--14:??",
  month =        nov,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1295231.1295235",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:49 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Microfluidics-based biochips, also referred to as
                 lab-on-a-chip, are devices that integrate
                 fluid-handling functions such as sample preparation,
                 analysis, separation, and detection. This emerging
                 technology combines electronics with biology to open
                 new application areas such as point-of-care diagnosis,
                 on-chip DNA analysis, and automated drug discovery. We
                 propose a design automation method for pin-constrained
                 biochips that manipulate nanoliter volumes of discrete
                 droplets on a microfluidic array. In contrast to the
                 direct-addressing scheme that has been studied thus far
                 in the literature, we assign a small number of
                 independent control pins to a large number of
                 electrodes in the biochip, thereby reducing design
                 complexity and product cost. The design procedure
                 relies on a droplet-trace-based array partitioning
                 scheme and an efficient pin assignment technique,
                 referred to as the ``Connect-5 algorithm.'' The
                 proposed method is evaluated using a set of multiplexed
                 bioassays.",
  acknowledgement = ack-nhfb,
  articleno =    "14",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "biochips; droplets; microfluidics; Physical design
                 automation",
}

@Article{Rad:2007:EAP,
  author =       "Reza M. P. Rad and Mohammad Tehranipoor",
  title =        "Evaluating area and performance of hybrid {FPGAs} with
                 nanoscale clusters and {CMOS} routing",
  journal =      j-JETC,
  volume =       "3",
  number =       "3",
  pages =        "15:1--15:??",
  month =        nov,
  year =         "2007",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1295231.1295236",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:03:49 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Advances in fabrication technology of nanoscale
                 devices such as nanowires, carbon nanotubes and
                 molecular switches provide new opportunities for
                 implementing cluster-based FPGAs. Extensive research is
                 needed to evaluate area and performance of FPGAs made
                 from these devices and compare with their CMOS
                 counterparts. In this work, we propose a hybrid FPGA
                 that uses nanoscale clusters with a functionality
                 similar to the clusters of traditional CMOS FPGAs. The
                 proposed cluster is constructed by a crossbar of
                 nanowires and can be configured to implement the
                 required LUTs and intracluster MUXes. A CMOS interface
                 is also proposed to provide configuration and memory
                 elements for the nanoscale cluster. In the proposed
                 architecture, inter-cluster routing remains at CMOS
                 scale. We have developed models for area and delay of
                 clusters and interconnects of the proposed hybrid FPGA.
                 FPGA tools are configured with these models and used to
                 synthesize and configure the benchmark circuits onto
                 the hybrid FPGAs with NiSi nanowires or nanotubes.
                 Experiments are conducted to evaluate and compare area
                 and performance of the hybrid FPGA and traditional CMOS
                 FPGA (scaled to 22nm). Up to 82\\% area reduction was
                 obtained from implementing MCNC benchmarks on the
                 hybrid FPGA. Performance of the hybrid FPGA is shown to
                 be close to that of CMOS FPGA.",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "CMOS; FPGA; Nanotechnology; performance; reliability",
}

@Article{Su:2008:HLS,
  author =       "Fei Su and Krishnendu Chakrabarty",
  title =        "High-level synthesis of digital microfluidic
                 biochips",
  journal =      j-JETC,
  volume =       "3",
  number =       "4",
  pages =        "1:1--1:??",
  month =        jan,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1324177.1324178",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:00 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Microfluidic biochips offer a promising platform for
                 massively parallel DNA analysis, automated drug
                 discovery, and real-time biomolecular recognition.
                 Current techniques for full-custom design of
                 droplet-based ``digital'' biochips do not scale well
                 for concurrent assays and for next-generation
                 system-on-chip (SOC) designs that are expected to
                 include microfluidic components. We propose a system
                 design methodology that attempts to apply classical
                 high-level synthesis techniques to the design of
                 digital microfluidic biochips. We focus here on the
                 problem of scheduling bioassay functions under resource
                 constraints. We first develop an optimal scheduling
                 strategy based on integer linear programming. However,
                 because the scheduling problem is NP-complete, we also
                 develop two heuristic techniques that scale well for
                 large problem instances. A clinical diagnostic
                 procedure, namely multiplexed in-vitro diagnostics on
                 human physiological fluids, is first used to illustrate
                 and evaluate the proposed method. Next, the synthesis
                 approach is applied to a protein assay, which serves as
                 a more complex bioassay application. The proposed
                 synthesis approach is expected to reduce human effort
                 and design cycle time, and it will facilitate the
                 integration of microfluidic components with
                 microelectronic components in next-generation SOCs.",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "biochips; High-level synthesis; microfluidics;
                 scheduling; system-on-chip",
}

@Article{VanMeter:2008:ADM,
  author =       "Rodney {Van Meter} and W. J. Munro and Kae Nemoto and
                 Kohei M. Itoh",
  title =        "Arithmetic on a distributed-memory quantum
                 multicomputer",
  journal =      j-JETC,
  volume =       "3",
  number =       "4",
  pages =        "2:1--2:??",
  month =        jan,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1324177.1324179",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:00 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "We evaluate the performance of quantum arithmetic
                 algorithms run on a distributed quantum computer (a
                 quantum multicomputer). We vary the node capacity and
                 I/O capabilities, and the network topology. The
                 tradeoff of choosing between gates executed remotely,
                 through ``teleported gates'' on entangled pairs of
                 qubits (telegate), versus exchanging the relevant
                 qubits via quantum teleportation, then executing the
                 algorithm using local gates (teledata), is examined. We
                 show that the teledata approach performs better, and
                 that carry-ripple adders perform well when the
                 teleportation block is decomposed so that the key
                 quantum operations can be parallelized. A node size of
                 only a few logical qubits performs adequately provided
                 that the nodes have two transceiver qubits. A linear
                 network topology performs acceptably for a broad range
                 of system sizes and performance parameters. We
                 therefore recommend pursuing small, high-I/O bandwidth
                 nodes and a simple network. Such a machine will run
                 Shor's algorithm for factoring large numbers
                 efficiently.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "quantum computer architecture; Quantum computing",
}

@Article{Ma:2008:MCE,
  author =       "Xiaojun Ma and Jing Huang and Fabrizio Lombardi",
  title =        "A model for computing and energy dissipation of
                 molecular {QCA} devices and circuits",
  journal =      j-JETC,
  volume =       "3",
  number =       "4",
  pages =        "3:1--3:??",
  month =        jan,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1324177.1324180",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:00 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Quantum-dot Cellular Automata is an emerging
                 technology that offers significant improvements over
                 CMOS. Recently QCA has been advocated as a technology
                 for implementing reversible computing. However,
                 existing tools for QCA design and evaluation have
                 limited capabilities. This paper presents a new
                 mechanical-based model for computing in QCA. By
                 avoiding a full quantum-thermodynamical calculation, it
                 offers a classical view of the principles of QCA
                 operation and can be used in evaluating energy
                 dissipation for reversible computing. The proposed
                 model is mechanically based and is applicable to
                 six-dot (neutrally charged) QCA cells for molecular
                 implementation. The mechanical model consists of a
                 sleeve of changing shape; four electrically charged
                 balls are connected by a stick that rotates around an
                 axle in the sleeve. The sleeve acts as a clocking unit,
                 while the angular position of the stick within the
                 changing shape of the sleeve, identifies the phase for
                 quasi-adiabatic switching. A thermodynamic analysis of
                 the proposed model is presented. The behaviors of
                 various QCA basic devices and circuits are analyzed
                 using the proposed model. It is shown that the proposed
                 model is capable of evaluating the energy consumption
                 for reversible computing at device and circuit levels
                 for molecular QCA implementation. As applicable to QCA,
                 two clocking schemes are also analyzed for energy
                 dissipation and performance (in terms of number of
                 clocking zones).",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "emerging technology; QCA; reversible computing;
                 thermodynamic analysis",
}

@Article{Chuang:2008:SRS,
  author =       "Min-Lun Chuang and Chun-Yao Wang",
  title =        "Synthesis of reversible sequential elements",
  journal =      j-JETC,
  volume =       "3",
  number =       "4",
  pages =        "4:1--4:??",
  month =        jan,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1324177.1324181",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:00 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "To construct a reversible sequential circuit,
                 reversible sequential elements are required. This work
                 presents novel designs of reversible sequential
                 elements such as the $D$ latch, $JK$ latch, and $T$
                 latch. Based on these reversible latches, we construct
                 the designs of the corresponding flip-flops. Then we
                 further discuss the physical implementations of our
                 designs based on electron waveguide $Y$-branch switch
                 technology. Test costs, including test generation and
                 test application, of reversible sequential circuits
                 with these reversible flip-flops are also discussed.
                 Compared with previous work, the implementation cost of
                 our new designs, including the number of gates and the
                 number of garbage outputs, is significantly reduced.
                 The number of gates in our designs is 47.4\\% of the
                 designs in previous work on average. The number of
                 garbage outputs in our designs is 25\\% of the designs
                 in previous work on average.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Reversible logic; sequential circuits; sequential
                 elements",
}

@Article{Metodi:2008:HLI,
  author =       "Tzvetan S. Metodi and Darshan D. Thaker and Andrew W.
                 Cross and Isaac L. Chuang and Frederic T. Chong",
  title =        "High-level interconnect model for the quantum logic
                 array architecture",
  journal =      j-JETC,
  volume =       "4",
  number =       "1",
  pages =        "1:1--1:??",
  month =        mar,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1330521.1330522",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:09 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "We summarize the main characteristics of the quantum
                 logic array (QLA) architecture with a careful look at
                 the key issues not described in the original conference
                 publications: primarily, the teleportation-based
                 logical interconnect. The design goal of the quantum
                 logic array architecture is to illustrate a model for a
                 large-scale quantum architecture that solves the
                 primary challenges of system-level reliability and data
                 distribution over large distances. The QLA's logical
                 interconnect design, which employs the quantum repeater
                 protocol, is in principle capable of supporting the
                 communication requirements for applications as large as
                 the factoring of a 2048-bit number using Shor's quantum
                 factoring algorithm. Our physical-level assumptions and
                 architectural component validations are based on the
                 trapped ion technology for implementing quantum
                 computing.",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "fault tolerance; large scale; QLA; quantum; Quantum
                 computer architecture design; teleportation",
}

@Article{Donald:2008:RLS,
  author =       "James Donald and Niraj K. Jha",
  title =        "Reversible logic synthesis with {Fredkin} and {Peres}
                 gates",
  journal =      j-JETC,
  volume =       "4",
  number =       "1",
  pages =        "2:1--2:??",
  month =        mar,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1330521.1330523",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:09 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Reversible logic has applications in low-power
                 computing and quantum computing. Most reversible logic
                 synthesis methods are tied to particular gate types,
                 and cannot synthesize large functions. This article
                 extends RMRLS, a reversible logic synthesis tool, to
                 include additional gate types. While classic RMRLS can
                 synthesize functions using NOT, CNOT, and $n$-bit
                 Toffoli gates, our work details the inclusion of
                 $n$-bit Fredkin and Peres gates. We find that these
                 additional gates reduce the average gate count for
                 three-variable functions from 6.10 to 4.56, and improve
                 the synthesis results of many larger functions, both in
                 terms of gate count and quantum cost.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Quantum computing; reversible logic",
}

@Article{Guiducci:2008:HPP,
  author =       "Carlotta Guiducci and Christine Nardini",
  title =        "High parallelism, portability, and broad
                 accessibility: {Technologies} for genomics",
  journal =      j-JETC,
  volume =       "4",
  number =       "1",
  pages =        "3:1--3:??",
  month =        mar,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1330521.1330524",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:09 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Biotechnology is an area of great innovations that
                 promises to have deep impact on everyday life thanks to
                 profound changes in biology, medicine, and health care.
                 This article will span from the description of the
                 biochemical principles of molecular biology to the
                 definition of the physics that supports the technology
                 and to the devices and algorithms necessary to observe
                 molecular events in a controlled, portable, and highly
                 parallel manner. Throughout this discussion, constant
                 attention will be given to the ultimate goals and
                 applications of these innovations as well as to the
                 related issues.",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "biosensors; Genomics; microarrays; point-of-care
                 diagnostics",
}

@Article{Narayanan:2008:E,
  author =       "Vijaykrishnan Narayanan",
  title =        "Editorial",
  journal =      j-JETC,
  volume =       "4",
  number =       "2",
  pages =        "4:1--4:??",
  month =        apr,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1350763.1350764",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:16 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Bahar:2008:IJA,
  author =       "R. Iris Bahar and Krishnendu Chakrabarty",
  title =        "Introduction to joint {ACM JETC\slash TODAES} special
                 issue on new, emerging, and specialized technologies",
  journal =      j-JETC,
  volume =       "4",
  number =       "2",
  pages =        "5:1--5:??",
  month =        apr,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1350763.1350765",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:16 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Kuo:2008:MSA,
  author =       "Shih-Hsien Kuo and Bruce Tidor and Jacob White",
  title =        "A meshless, spectrally accurate, integral equation
                 solver for molecular surface electrostatics",
  journal =      j-JETC,
  volume =       "4",
  number =       "2",
  pages =        "6:1--6:??",
  month =        apr,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1350763.1350766",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:16 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The need to determine electrostatic fields in domains
                 bounded by molecular surfaces arises in a number of
                 nanotechnology applications including: biomolecule
                 design, carbon nanotube simulation, and molecular
                 electron transport analysis. Molecular surfaces are
                 typically smooth, without the corners common in
                 electrical interconnect problems, but are often so
                 geometrically complicated that numerical evaluation of
                 the associated electrostatic fields is extremely
                 time-consuming. In this paper we describe and
                 demonstrate a meshless spectrally-accurate integral
                 equation method that only requires a description of the
                 molecular surface in the form of a collection of
                 surface points. Our meshless method is a synthesis of
                 techniques, suitably adapted, including: spherical
                 harmonic surface interpolation, spectral-element-like
                 integral equation discretization, integral
                 desingularization via variable transformation, and
                 matrix-implicit iterative matrix solution. The spectral
                 accuracy of this combined method is verified using
                 analytically solvable sphere and ellipsoid problems,
                 and then its accuracy and efficiency is demonstrated
                 numerically by solving capacitance and coupled
                 Poisson\slash linearized Poisson--Boltzmann problems
                 associated with a commonly used model of a molecule in
                 solution. The results demonstrate that for a tolerance
                 of 10$^{-3}$ this new approach reduces the number of
                 unknowns by as much as two orders of magnitude over the
                 more commonly used flat panel methods.",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "integral equation; meshless; Poisson--Boltzmann
                 equation; spectral method",
}

@Article{Deng:2008:CNT,
  author =       "Jie Deng and Albert Lin and Gordon C. Wan and H.-S.
                 Philip Wong",
  title =        "Carbon nanotube transistor compact model for circuit
                 design and performance optimization",
  journal =      j-JETC,
  volume =       "4",
  number =       "2",
  pages =        "7:1--7:??",
  month =        apr,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1350763.1350767",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:16 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this paper, we describe the development of the
                 Stanford University Carbon Nanotube FET (CNFET) Compact
                 Model. The CNFET Model is a circuit-compatible, compact
                 model which describes enhancement-mode, CMOS-like
                 CNFETs. It can be used to simulate both functionality
                 and performance of large-scale circuits with hundreds
                 of CNFETs. To produce realistic and relevant results,
                 the model accounts for several practical non-idealities
                 such as scattering in the near-ballistic channel,
                 effects of the source/drain extension region, and
                 charge-screening for multiple-nanotube CNFETs. The
                 model also includes a full transcapacitance network for
                 more accurate transient and AC results. The Stanford
                 University CNFET Model is implemented in both HSPICE
                 macro language and VerilogA. The VerilogA
                 implementation shows speedups of roughly $7 \times$ --
                 $15 \times$ over HSPICE. Applications of the model
                 suggest that $n$- and $p$-CNFETs will have $6 \times$
                 and $13 \times$ speed advantage over Si $n$- and
                 $p$-MOSFETs respectively at the 32nm node, and that a
                 CNT density of 250 CNTs/$\mu$m is ideal for
                 multiple-nanotube gates. Such a compact CNFET model
                 will be absolutely essential in ushering in the Design
                 Era of CNFET circuits as carbon nanotube technology
                 outgrows its ``science discovery'' phase.",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "carbon nanotube FET; CNT; compact model; HSPICE;
                 VerilogA",
}

@Article{Carmona:2008:FMA,
  author =       "Josep Carmona and Jordi Cortadella and Yousuke Takada
                 and Ferdinand Peper",
  title =        "Formal methods for the analysis and synthesis of
                 nanometer-scale cellular arrays",
  journal =      j-JETC,
  volume =       "4",
  number =       "2",
  pages =        "8:1--8:??",
  month =        apr,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1350763.1350768",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:16 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Nanometer-scale structures suitable for computing have
                 been investigated by several research groups in recent
                 years. A common feature of these structures is their
                 dynamic evolution through cascaded local interactions
                 embedded on a discrete grid. Finding configurations
                 capable of conducting computations is a task that often
                 requires tedious experiments in laboratories. Formal
                 methods --- though used extensively for the
                 specification and verification of software and hardware
                 computing systems --- are virtually unexplored with
                 respect to computational structures at atomic scales.
                 This paper presents a systematic approach toward the
                 application of formal methods in this context, using
                 techniques like abstraction, model-checking, and
                 symbolic representations of states to explore and
                 discover computational structures. The proposed
                 techniques are applied to a system of CO molecules on a
                 grid of Copper atoms, resulting in the design of a
                 complete library of combinational logic gates based on
                 this molecular system. The techniques are also applied
                 on (more general) systems of cellular automata that
                 employ an asynchronous mode of timing. The use of
                 formal methods may narrow the gap between Physical
                 Chemistry and Computer Science, allowing the
                 description of interactions of nanometer scale systems
                 on a level of abstraction suitable to devise computing
                 devices.",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "cellular array; model checking; Nanocomputing;
                 symbolic techniques",
}

@Article{Crocker:2008:MQD,
  author =       "Michael Crocker and Michael Niemier and X. Sharon Hu
                 and Marya Lieberman",
  title =        "Molecular {QCA} design with chemically reasonable
                 constraints",
  journal =      j-JETC,
  volume =       "4",
  number =       "2",
  pages =        "9:1--9:??",
  month =        apr,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1350763.1350769",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Fri Jun 20 11:04:16 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this article we examine the impacts of the
                 fundamental constraints required for circuits and
                 systems made from molecular Quantum-dot Cellular
                 Automata (QCA) devices. Our design constraints are
                 ``chemically reasonable'' in that we consider the
                 characteristics and dimensions of devices and
                 scaffoldings that have actually been fabricated. This
                 work is a necessary first step for any work in QCA CAD,
                 and can also help shape experiments in the physical
                 sciences for emerging, nano-scale devices. Our work
                 shows that QCA circuits, scaffoldings, substrates, and
                 devices should all be considered simultaneously.
                 Otherwise, there is a very real possibility that the
                 devices and scaffoldings that are eventually
                 manufactured will result in devices that only work in
                 isolation. ``Chemically reasonable'' also means that
                 expected manufacturing defects must be considered. In
                 our simulations we introduce defects associated with
                 self-assembled systems into various designs to begin to
                 define manufacturing tolerances. This work is
                 especially timely as experimentalists are beginning to
                 work on merging experimental tracks that address
                 devices and scaffolds --- and the end result should
                 facilitate correct logical operations.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "defects; Nanotechnology; physical simulation;
                 quantum-dot cellular automata",
}

@Article{Lebeck:2008:IDS,
  author =       "Alvin R. Lebeck and Krishnendu Chakrabarty",
  title =        "Introduction to {DAC 2007} special section",
  journal =      j-JETC,
  volume =       "4",
  number =       "3",
  pages =        "10:1--10:??",
  month =        aug,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1389089.1389090",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Sep 4 14:23:10 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "10",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Xu:2008:IDR,
  author =       "Tao Xu and Krishnendu Chakrabarty",
  title =        "Integrated droplet routing and defect tolerance in the
                 synthesis of digital microfluidic biochips",
  journal =      j-JETC,
  volume =       "4",
  number =       "3",
  pages =        "11:1--11:??",
  month =        aug,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1389089.1389091",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Sep 4 14:23:10 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Microfluidic biochips are revolutionizing
                 high-throughput DNA sequencing, immunoassays, and
                 clinical diagnostics. As high-throughput bioassays are
                 mapped to digital microfluidic platforms, the need for
                 design automation techniques is being increasingly
                 felt. Moreover, as most applications of biochips are
                 safety-critical in nature, defect tolerance is an
                 essential system attribute. Several synthesis tools
                 have recently been proposed for the automated design of
                 biochips from the specifications of laboratory
                 protocols. However, only a few of these tools address
                 the problem of defect tolerance. In addition, most of
                 these methods do not consider the problem of droplet
                 routing in microfluidic arrays. These methods typically
                 rely on postsynthesis droplet routing to implement
                 biochemical protocols. Such an approach is not only
                 time consuming, but also imposes an undue burden on the
                 chip user. Postsynthesis droplet routing does not
                 guarantee that feasible droplet pathways can be found
                 for area-constrained biochip layouts; nonroutable
                 fabricated biochips must be discarded. We present a
                 synthesis tool that integrates defect tolerance and
                 droplet routing in the design flow. Droplet
                 routability, defined as the ease with which droplet
                 pathways can be determined, is estimated and integrated
                 in the synthesis procedure. Presynthesis and
                 postsynthesis defect-tolerance methods are also
                 presented. We use a large-scale protein assay as a case
                 study to evaluate the proposed synthesis method.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "biochips; microfluidics; module placement; physical
                 design automation",
}

@Article{Huang:2008:RAF,
  author =       "Tsung-Ching Huang and Kwang-Ting (Tim) Cheng and
                 Huai-Yuan Tseng and Chen-Pang Kung",
  title =        "Reliability analysis for flexible electronics: {Case}
                 study of integrated {a-Si:H} {TFT} scan driver",
  journal =      j-JETC,
  volume =       "4",
  number =       "3",
  pages =        "12:1--12:??",
  month =        aug,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1389089.1389092",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Sep 4 14:23:10 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Flexible electronics fabricated on thin-film,
                 lightweight, and bendable substrates (e.g., plastic)
                 have great potential for novel applications in consumer
                 electronics such as flexible displays, e-paper, and
                 smart labels; however, the key elements, namely
                 thin-film transistors (TFTs), for implementing flexible
                 circuits often suffer from electrical instability.
                 Therefore, thorough reliability analysis is critical
                 for flexible circuit design to ensure that the circuit
                 will operate reliably throughout its lifetime. In this
                 article we propose a methodology for reliability
                 simulation of hydrogenated amorphous silicon (a-Si:H)
                 TFT circuits. We show that: (1) the threshold voltage
                 ({\em V$_{TH}$\/}) shift of a single TFT can be
                 estimated by analyzing its operating conditions; and
                 (2) the circuit lifetime can be predicted accordingly
                 by using SPICE-like simulators with proper modeling. We
                 also propose an algorithm to reduce the simulation time
                 by orders of magnitude, with good prediction accuracy.
                 To validate our analytical model and simulation
                 methodology, we compare simulation results with the
                 actual circuit measurements of an integrated a-Si:H TFT
                 scan driver fabricated on a glass substrate and we
                 demonstrate very good consistency.",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "amorphous hydrogenated silicon (a-Si:H); flexible
                 electronics; reliability; scan driver; thin-film
                 transistor; threshold voltage",
}

@Article{Li:2008:ADP,
  author =       "Jing Li and Aditya Bansal and Swarop Ghosh and Kaushik
                 Roy",
  title =        "An alternate design paradigm for low-power, low-cost,
                 testable hybrid systems using scaled {LTPS TFTs}",
  journal =      j-JETC,
  volume =       "4",
  number =       "3",
  pages =        "13:1--13:??",
  month =        aug,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1389089.1389093",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Sep 4 14:23:10 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "This article presents a holistic hybrid design
                 methodology for low-power, low-cost, testable digital
                 designs using low-temperature polycrystalline-silicon
                 thin-film transistors (LTPS TFTs). An alternate scaling
                 rule under low thermal budget (due to flexible
                 substrate) is developed to improve the performance of
                 TFTs in the presence of process variation. We
                 demonstrate that LTPS TFTs can be further optimized for
                 ultralow-power subthreshold operation with performances
                 comparable to contemporary single-crystal
                 silicon-on-insulator (c-Si SOI) devices after process
                 optimization. The optimized LTPS TFTs with high current
                 drivability and less variability can comprise a
                 promising low-cost option to augment Si CMOS
                 technology, opening up a plethora of new hybrid 3D
                 applications. We illustrate one such application: IC
                 testing. Testing of complex VLSI systems is a prime
                 concern due to design cost of DFT circuits, area/delay
                 overheads, and poor test confidence. To harness the
                 benefits of TFT technology, a novel low-power,
                 process-tolerant, generic, and reconfigurable test
                 structure designed using LTPS TFTs is proposed to
                 reduce the test cost, as well as to improve
                 diagnosability and verifiability, of complex VLSI
                 systems. Due to proper optimization of TFT devices, the
                 proposed test structure consumes low power but operates
                 with reasonable performance. Furthermore, the test
                 circuits do not consume any silicon area because they
                 can be integrated on-chip using 3D technology. Since
                 the test architecture is reconfigurable, this
                 eliminates the need to redesign built-in-self-test
                 (BIST) components that may vary from one processor
                 generation to another. We have developed test
                 structures using 200nm TFT devices and evaluated them
                 on designs implemented in 130nm bulk CMOS. For circuit
                 simulations, we have developed a SPICE-compatible model
                 for TFT devices. The BIST components designed using the
                 test structures operate at 0.8--4.3 GHz (compared to
                 8.2 GHz in bulk CMOS) with low power consumption. The
                 enhanced scan cells partially implemented in TFT (3D
                 hybrid design) consume \sim 24\% less power and \sim
                 15--20\% less area of Si die compared to conventional
                 bulk-Si design (2D planar design), with minimal delay
                 overhead.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "3D integration; BIST; DFT; generic; grain boundary
                 (GB); hybrid system; inherent variation;
                 low-temperature polycrystalline silicon (LTPS);
                 reconfigurable; thin-film transistor (TFT)",
}

@Article{Rad:2008:SNA,
  author =       "Reza Rad and Mohammad Tehranipoor",
  title =        "{SCT}: {A} novel approach for testing and configuring
                 nanoscale devices",
  journal =      j-JETC,
  volume =       "4",
  number =       "3",
  pages =        "14:1--14:??",
  month =        aug,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1389089.1389094",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Sep 4 14:23:10 MDT 2008",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Novel strategies are necessary to efficiently test and
                 configure emerging reconfigurable nanoscale devices, in
                 addition to providing defect tolerance. This is mainly
                 due to the high defect densities that are expected for
                 these devices. Among different approaches,
                 reconfiguration-based defect avoidance has proven to be
                 a practical solution. However, configuration time, test
                 time, and defect-map size remain among the major
                 challenges for these new devices. In this article, we
                 propose a new approach (called SCT) that simultaneously
                 performs test and configuration. The proposed method
                 uses a built-in self-test (BIST) scheme for test and
                 defect tolerance. The method is based on testing
                 reconfigurable nanoblocks at the time of implementing a
                 function of a desired application on that block. The
                 SCT method considerably reduces the total test and
                 configuration time. It also eliminates the need for
                 storing the location of defects in a defect map on- or
                 off-chip. The presented probabilistic analysis results
                 show the effectiveness of this method in terms of test
                 and configuration time for architectures with rich
                 interconnect resources. Also, a Verilog simulation
                 model is developed for crossbar-based
                 nano-architectures. This model is used to implement
                 several MCNC benchmarks based on the proposed SCT
                 method. The simulation results demonstrate efficiency
                 of the method in terms of test time and yield under
                 different defect rates.",
  acknowledgement = ack-nhfb,
  articleno =    "14",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "configuration and testing; crossbar; fault tolerance;
                 nanowire; reconfigurable nanoscale devices",
}

@Article{Xie:2008:ESI,
  author =       "Yuan Xie and Jason Cong and Paul Franzon",
  title =        "Editorial: {Special} issue on {$3$D} integrated
                 circuits and microarchitectures",
  journal =      j-JETC,
  volume =       "4",
  number =       "4",
  pages =        "15:1--15:??",
  month =        oct,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1412587.1412588",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:22:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Kgil:2008:PUS,
  author =       "Taeho Kgil and Ali Saidi and Nathan Binkert and Steve
                 Reinhardt and Krisztian Flautner and Trevor Mudge",
  title =        "{PicoServer}: {Using} {$3$D} stacking technology to
                 build energy efficient servers",
  journal =      j-JETC,
  volume =       "4",
  number =       "4",
  pages =        "16:1--16:??",
  month =        oct,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1412587.1412589",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:22:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "This article extends our prior work to show that a
                 straightforward use of 3D stacking technology enables
                 the design of compact energy-efficient servers. Our
                 proposed architecture, called PicoServer, employs 3D
                 technology to bond one die containing several simple,
                 slow processing cores to multiple memory dies
                 sufficient for a primary memory. The multiple memory
                 dies are composed of DRAM. This use of 3D stacks
                 readily facilitates wide low-latency buses between
                 processors and memory. These remove the need for an L2
                 cache allowing its area to be re-allocated to
                 additional simple cores. The additional cores allow the
                 clock frequency to be lowered without impairing
                 throughput. Lower clock frequency means that thermal
                 constraints, a concern with 3D stacking, are easily
                 satisfied. We extend our original analysis on
                 PicoServer to include: (1) a wider set of server
                 workloads, (2) the impact of multithreading, and (3)
                 the on-chip DRAM architecture and system memory usage.
                 PicoServer is intentionally simple, requiring only the
                 simplest form of 3D technology where die are stacked on
                 top of one another. Our intent is to minimize risk of
                 introducing a new technology (3D) to implement a class
                 of low-cost, low-power compact server architectures.",
  acknowledgement = ack-nhfb,
  articleno =    "16",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "3D stacking technology; chip multiprocessor;
                 full-system simulation; Low power; Tier-1/2/3 server",
}

@Article{Ma:2008:IEF,
  author =       "Yuchun Ma and Yongxiang Liu and Eren Kursun and Glenn
                 Reinman and Jason Cong",
  title =        "Investigating the effects of fine-grain
                 three-dimensional integration on microarchitecture
                 design",
  journal =      j-JETC,
  volume =       "4",
  number =       "4",
  pages =        "17:1--17:??",
  month =        oct,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1412587.1412590",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:22:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this article we propose techniques that enable
                 efficient exploration of the 3D design space, where
                 each logical block can span more than one silicon
                 layer. Fine-grain 3D integration provides reduced
                 intrablock wire delay as well as improved power
                 consumption. However, the corresponding power and
                 performance advantage is usually underutilized, since
                 various implementations of multilayer blocks require
                 novel physical design and microarchitecture
                 infrastructure to explore 3D microarchitecture design
                 space. We develop a cubic packing engine which can
                 simultaneously optimize physical and architectural
                 design for efficient vertical integration. This
                 technique selects the individual unit designs from a
                 set of single-layer or multilayer implementations to
                 get the best microarchitectural design in terms of
                 performance, temperature, or both. Our experimental
                 results using a design driver of a high-performance
                 superscalar processor show a 36\% performance
                 improvement over traditional 2D for 2--4 layers and
                 14\% over 3D with single-layer unit implementations.
                 Since thermal characteristics of 3D integrated circuits
                 are among the main challenges, thermal-aware
                 floorplanning and thermal via insertion techniques are
                 employed to keep the peak temperatures below
                 threshold.",
  acknowledgement = ack-nhfb,
  articleno =    "17",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "3D integration; 3D packing; microarchitecture;
                 thermal",
}

@Article{Zhan:2008:AMA,
  author =       "Yong Zhan and Sachin S. Sapatnekar",
  title =        "Automated module assignment in stacked-{Vdd} designs
                 for high-efficiency power delivery",
  journal =      j-JETC,
  volume =       "4",
  number =       "4",
  pages =        "18:1--18:??",
  month =        oct,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1412587.1412591",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:22:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "With aggressive reductions in feature sizes and the
                 integration of multiple functionalities on the same
                 die, bottlenecks due to I/O pin limitations have become
                 a critical issue in today's VLSI designs, especially
                 for 3D IC technologies. To alleviate the pin limitation
                 problem, a stacked-Vdd circuit paradigm has recently
                 been proposed in the literature. However, for a circuit
                 designed using this paradigm, a significant amount of
                 power may be wasted if modules are not carefully
                 assigned to different Vdd domains. In this article, we
                 present a partition-based algorithm for efficiently
                 assigning modules at the floorplanning level, so as to
                 reuse currents between Vdd domains and minimize the
                 power wasted during the operation of the circuit.
                 Experimental results on both 3D and 2D ICs show that
                 compared with assigning modules to different Vdd
                 domains using enumeration and simulated annealing, our
                 algorithm can generate circuits with competitive power
                 and IR noise performance, while being orders of
                 magnitude faster.",
  acknowledgement = ack-nhfb,
  articleno =    "18",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Ferri:2008:PYM,
  author =       "Cesare Ferri and Sherief Reda and R. Iris Bahar",
  title =        "Parametric yield management for {$3$D} {ICs}: {Models}
                 and strategies for improvement",
  journal =      j-JETC,
  volume =       "4",
  number =       "4",
  pages =        "19:1--19:??",
  month =        oct,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1412587.1412592",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:22:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Three-Dimensional (3D) Integrated Circuits (ICs) that
                 integrate die with Through-Silicon Vias (TSVs) promise
                 to continue system and functionality scaling beyond the
                 traditional geometric 2D device scaling. 3D integration
                 also improves the performance of ICs by reducing the
                 communication time between different chip components
                 through the use of short TSV-based vertical wires. This
                 reduction is particularly attractive in processors
                 where it is desirable to reduce the access time between
                 the main logic die and the L2 cache or the main memory
                 die. Process variations in 2D ICs lead to a drop in
                 parametric yield (as measured by speed, leakage and
                 sales profits), which forces manufacturers to speed bin
                 their chips and to sell slow chips at reduced prices.
                 In this paper we develop a model to quantify the impact
                 of process variations on the parametric yield of 3D
                 ICs, and then we propose a number of integration
                 strategies that use a graph-theoretic framework to
                 maximize the performance, parametric yield and profits
                 of 3D ICs. Comparing our proposed strategies to current
                 yield-oblivious methods, it is demonstrated that it is
                 possible to increase the number of 3D ICs in the
                 fastest speed bins by almost 2\times , while
                 simultaneously reducing the number of slow ICs by
                 29.4\%. This leads to an improvement in performance by
                 up to 6.45\% and an increase of about 12.48\% in total
                 sales revenue using up-to-date market price models.",
  acknowledgement = ack-nhfb,
  articleno =    "19",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "3D integration; leakage; performance; process
                 variations; yield management",
}

@Article{Miyakawa:2008:MST,
  author =       "Nobuaki Miyakawa and Eiri Hashimoto and Takanori
                 Maebashi and Natsuo Nakamura and Yutaka Sacho and
                 Shigeto Nakayama and Shinjiro Toyoda",
  title =        "Multilayer stacking technology using wafer-to-wafer
                 stacked method",
  journal =      j-JETC,
  volume =       "4",
  number =       "4",
  pages =        "20:1--20:??",
  month =        oct,
  year =         "2008",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1412587.1412593",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:22:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "We have developed a new three-dimensional stacking
                 technology using the wafer-to-wafer stacked method.
                 Electrical conductivity between each wafer is almost
                 100\% and contact resistance is less than 0.7\Omega
                 between a through-silicon via (TSV) and a microbump. We
                 have also created a prototype of a three-layer stacking
                 device using our technology, where each wafer for the
                 stacking is fabricated by using 0.18um CMOS technology
                 based on 8-inch wafers. The device is operated by two
                 times the frequency of the multichip module (MCM)
                 device case using a two-dimensional device with
                 identical functions and minimally different power
                 consumption. The yields obtained from the results
                 comprising all functional tests are over 60\%.",
  acknowledgement = ack-nhfb,
  articleno =    "20",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "3D integration; design; hardware; stacking process",
}

@Article{Shukla:2009:GEI,
  author =       "Sandeep Shukla",
  title =        "Guest editorial: {IEEE\slash ACM} Symposium on
                 Nanoscale Architectures {(NANOARCH07)}",
  journal =      j-JETC,
  volume =       "5",
  number =       "1",
  pages =        "1:1--1:??",
  month =        jan,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1482613.1482614",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:14 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Wang:2009:TAR,
  author =       "Shuo Wang and Lei Wang and Faquir Jain",
  title =        "Towards achieving reliable and high-performance
                 nanocomputing via dynamic redundancy allocation",
  journal =      j-JETC,
  volume =       "5",
  number =       "1",
  pages =        "2:1--2:??",
  month =        jan,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1482613.1482615",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:14 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Nanoelectronic devices are considered to be the
                 computational fabrics for the emerging nanocomputing
                 systems due to their ultra-high speed and integration
                 density. However, the imperfect bottom-up self-assembly
                 fabrication leads to excessive defects that have become
                 a barrier for achieving reliable computing. In
                 addition, transient errors continue to be a problem.
                 The massive parallelism rendered by nanoscale
                 integration opens up new opportunities but also poses
                 challenges on how to manage such massive resources for
                 reliable and high-performance computing. In this paper,
                 we propose a nanoarchitecture solution to address these
                 emerging challenges. By using dynamic redundancy
                 allocation, the massive parallelism is exploited to
                 jointly achieve fault (defect/error) tolerance and high
                 performance. Simulation results demonstrate the
                 effectiveness of the proposed technique under a range
                 of fault rates and operating conditions.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "hardware reliability; Nanoscale architecture;
                 performance; redundancy allocation; redundant design",
}

@Article{Wang:2009:ENP,
  author =       "Z. F. Wang and Huaixiu Zheng and Q. W. Shi and Jie
                 Chen",
  title =        "Emerging nanodevice paradigm: {Graphene-based}
                 electronics for nanoscale computing",
  journal =      j-JETC,
  volume =       "5",
  number =       "1",
  pages =        "3:1--3:??",
  month =        jan,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1482613.1482616",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:14 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The continued miniaturization of silicon-based
                 electronic circuits is fast approaching its physical
                 limitations. It is unlikely that advances in
                 miniaturization, following the so-called Moore's Law,
                 can continue in the foreseeable future. Nanoelectronics
                 has to go beyond silicon technology. New device
                 paradigms based on nanoscale materials, such as
                 molecular electronic devices, spin devices and
                 carbon-based devices, will emerge. In this article, we
                 introduce a nanodevice paradigm: graphene
                 nanoelectronics. Due to its unique quantum effects and
                 electronic properties, researchers predict that
                 graphene-based devices may replace carbon nanotube
                 devices and become major building blocks for future
                 nanoscale computing. To manifest its unique electronic
                 properties, we present some of our recent designs,
                 namely a graphene-based switch, a negative differential
                 resistance (NDR) device and a random access memory
                 array (RAM). Since these basic devices are the building
                 blocks for large-scale circuits, our findings can help
                 researchers construct useful computing systems and
                 study graphene-based circuit performance in the
                 future.",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Graphene device; memory structure; negative
                 differential resistance; tight-binding model",
}

@Article{Taskin:2009:SRB,
  author =       "Baris Taskin and Andy Chiu and Jonathan Salkind and
                 Daniel Venutolo",
  title =        "A shift-register-based {QCA} memory architecture",
  journal =      j-JETC,
  volume =       "5",
  number =       "1",
  pages =        "4:1--4:??",
  month =        jan,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1482613.1482617",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:14 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "A quantum-dot cellular automata (QCA) design of an $n
                 \times m$-bit, shift-register-based memory architecture
                 is presented. The architecture maintains data at a
                 stable conformation, which is contrary to traditional
                 data in-motion concept for QCA architectures. The
                 memory architecture is based on an existing
                 dual-phase-synchronized, line-based, one-bit QCA memory
                 cell building block that provides size and latency
                 improvements over other known one-bit memory cells
                 through its novel clocking scheme. Read/write latencies
                 up to \sim 2X lower than the existing tile-based
                 architecture with three-phase, line-based memory cells
                 are obtained. Simulations with QCADesigner and HDLQ are
                 performed on a sample $4 \times 8$ bit memory
                 architecture implementation.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "clocking; memory design; Quantum-dot cellular
                 automata",
}

@Article{Huo:2009:SBN,
  author =       "Dennis Huo and Qiaoyan Yu and David Wolpert and Paul
                 Ampadu",
  title =        "A simulator for ballistic nanostructures in a {$2$-D}
                 electron gas",
  journal =      j-JETC,
  volume =       "5",
  number =       "1",
  pages =        "5:1--5:??",
  month =        jan,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1482613.1482618",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:14 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "A multipurpose simulator for ballistic nanostructures,
                 based on classical mechanics of electrons at the Fermi
                 level, has been successfully implemented. Despite the
                 simplicity of the model, the simulator successfully
                 reproduces a number of experimental results, and is
                 shown to consistently match observed current-voltage
                 characteristics and magnetoresistance phenomena. The
                 simulator results provide design guidelines for devices
                 which operate on ballistic transport principles. Using
                 the simulator, preliminary logic structures have been
                 designed based on the ballistic deflection
                 transistor.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "2DEG; Ballistic transport; nanoelectronic device;
                 transistor",
}

@Article{Bahar:2009:ISS,
  author =       "R. Iris Bahar",
  title =        "Introduction to special section: {Best} of {NANOARCH
                 2008}",
  journal =      j-JETC,
  volume =       "5",
  number =       "2",
  pages =        "6:1--6:??",
  month =        jul,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1543438.1543439",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:24 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Mishra:2009:LPF,
  author =       "Prateek Mishra and Anish Muttreja and Niraj K. Jha",
  title =        "Low-power {FinFET} circuit synthesis using multiple
                 supply and threshold voltages",
  journal =      j-JETC,
  volume =       "5",
  number =       "2",
  pages =        "7:1--7:??",
  month =        jul,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1543438.1543440",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:24 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "According to Moore's law, the number of transistors in
                 a chip doubles every 18 months. The increased
                 transistor-count leads to increased power density.
                 Thus, in modern circuits, power efficiency is a central
                 determinant of circuit efficiency. With scaling,
                 leakage power accounts for an increasingly larger
                 portion of the total power consumption in deep
                 submicron technologies (>40\%).\par

                 FinFET technology has been proposed as a promising
                 alternative to deep submicron bulk CMOS technology,
                 because of its better scalability, short-channel
                 characteristics, and ability to suppress leakage
                 current and mitigate device-to-device variability when
                 compared to bulk CMOS. The subthreshold slope of a
                 FinFET is approximately 60mV which is close to
                 ideal.\par

                 In this article, we propose a methodology for low-power
                 FinFET based circuit synthesis. A mechanism called TCMS
                 (Threshold Control through Multiple Supply Voltages)
                 was previously proposed for improving the power
                 efficiency of FinFET based global interconnects. We
                 propose a significant generalization of TCMS to the
                 design of any logic circuit. This scheme represents a
                 significant divergence from the conventional multiple
                 supply voltage schemes considered in the past. It also
                 obviates the need for voltage level-converters. We
                 employ accurate delay and power estimates using table
                 look-up methods based on HSPICE simulations for supply
                 voltage and threshold voltage optimization.
                 Experimental results demonstrate that TCMS can provide
                 power savings of 67.6\% and device area savings of
                 65.2\% under relaxed delay constraints. Two other
                 variants of TCMS are also proposed that yield similar
                 benefits. We compare our scheme to extended cluster
                 voltage scaling (ECVS), a popular dual- {\em
                 V$_{dd}$\/} scheme presented in the literature. ECVS
                 makes use of voltage level-converters. Even when it is
                 assumed that these level-converters have zero delay,
                 thus significantly favoring ECVS in time-constrained
                 power optimization, TCMS still outperforms ECVS.",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "linear programming; Low-power; synthesis; TCMS",
}

@Article{Crocker:2009:DFQ,
  author =       "Michael Crocker and X. Sharon Hu and Michael
                 Niemier",
  title =        "Defects and faults in {QCA}-based {PLAs}",
  journal =      j-JETC,
  volume =       "5",
  number =       "2",
  pages =        "8:1--8:??",
  month =        jul,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1543438.1543441",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:24 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Defect tolerance will be critical in any system with
                 nanoscale feature sizes. This article examines some
                 fundamental aspects of defect tolerance for a
                 reconfigurable system based on Quantum-dot Cellular
                 Automata (QCA). We analyze a novel, QCA-based,
                 Programmable Logic Array (PLA) structure, develop an
                 implementation independent fault model, and discuss how
                 expected defects and faults might affect yield. Within
                 this context, we introduce techniques for mapping
                 Boolean logic functions to a defective QCA-based PLA.
                 Simulation results show that our new mapping techniques
                 can achieve higher yields than existing techniques.",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "defects; faults; logic mapping; Nanotechnology;
                 quantum-dot cellular automata",
}

@Article{Wu:2009:SCD,
  author =       "Xiaoxia Wu and Paul Falkenstern and Krishnendu
                 Chakrabarty and Yuan Xie",
  title =        "Scan-chain design and optimization for
                 three-dimensional integrated circuits",
  journal =      j-JETC,
  volume =       "5",
  number =       "2",
  pages =        "9:1--9:??",
  month =        jul,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1543438.1543442",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:24 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Scan chains are widely used to improve the testability
                 of integrated circuit (IC) designs and to facilitate
                 fault diagnosis. For traditional 2D IC design, a number
                 of design techniques have been proposed in the
                 literature for scan-chain routing and scan-cell
                 partitioning. However, these techniques are not
                 effective for three-dimensional (3D) technologies,
                 which have recently emerged as a promising means to
                 continue technology scaling. In this article, we
                 propose two techniques for designing scan chains in 3D
                 ICs, with given constraints on the number of
                 through-silicon-vias (TSVs). The first technique is
                 based on a genetic algorithm (GA), and it addresses the
                 ordering of cells in a single scan chain. The second
                 optimization technique is based on integer linear
                 programming (ILP); it addresses single-scan-chain
                 ordering as well as the partitioning of scan flip-flops
                 into multiple scan chains. We compare these two methods
                 by conducting experiments on a set of ISCAS'89
                 benchmark circuits. The first conclusion obtained from
                 the results is that 3D scan-chain optimization achieves
                 significant wire-length reduction compared to 2D
                 counterparts. The second conclusion is that the
                 ILP-based technique provides lower bounds on the
                 scan-chain interconnect length for 3D ICs, and it
                 offers considerable reduction in wire-length compared
                 to the GA-based heuristic method.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "3D ICs; genetic algorithm; integer linear programming;
                 LP relaxation; randomized rounding; scan-chain design",
}

@Article{Datta:2009:EPT,
  author =       "Siddhartha Datta and Bharat Joshi and Arun Ravindran
                 and Arindam Mukherjee",
  title =        "Efficient parallel testing and diagnosis of digital
                 microfluidic biochips",
  journal =      j-JETC,
  volume =       "5",
  number =       "2",
  pages =        "10:1--10:??",
  month =        jul,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1543438.1543443",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:24 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Microfluidics-based biochips consist of microfluidic
                 arrays on rigid substrates through which movement of
                 fluids is tightly controlled to facilitate biological
                 reactions. Biochips are soon expected to revolutionize
                 biosensing, clinical diagnostics, environmental
                 monitoring, and drug discovery. Critical to the
                 deployment of the biochips in such diverse areas is the
                 dependability of these systems. Thus robust testing and
                 diagnosis techniques are required to ensure adequate
                 level of system dependability. Due to the underlying
                 mixed technology and mixed energy domains, such
                 biochips exhibit unique failure mechanisms and defects.
                 In this article efficient parallel testing and
                 diagnosis algorithms are presented that can detect and
                 locate single as well as multiple faults in a
                 microfluidic array without flooding the array, a
                 problem that has hampered realistic implementation of
                 several existing strategies. The fault diagnosis
                 algorithms are well suited for built-in self-test that
                 could drastically reduce the operating cost of
                 microfluidic biochip. Also, the proposed alogirthms can
                 be used both for testing and fault diagnosis during
                 field operation as well as increasing yield during the
                 manufacturing phase of the biochip. Furthermore, these
                 algorithms can be applied to both online and offline
                 testing and diagnosis. Analytical results suggest that
                 these strategies that can be used to design highly
                 dependable biochip systems.",
  acknowledgement = ack-nhfb,
  articleno =    "10",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "defect tolerance; droplet flooding; fault tolerance;
                 Microfluidic biochip; microfluidics; multiple faults;
                 reconfigurability; testing",
}

@Article{Tahoori:2009:LOD,
  author =       "Mehdi B. Tahoori",
  title =        "Low-overhead defect tolerance in crossbar
                 nanoarchitectures",
  journal =      j-JETC,
  volume =       "5",
  number =       "2",
  pages =        "11:1--11:??",
  month =        jul,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1543438.1543444",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:24 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "It is anticipated that the number of defects in
                 nanoscale devices fabricated using bottom-up
                 self-assembly process is significantly higher than that
                 for CMOS devices fabricated by conventional top-down
                 lithography patterning. This is mainly because of
                 inherent lack of control in self-assembly fabrication
                 as well as atomic scale of devices. The goal of defect
                 tolerance, as an integral part of nano computing, is to
                 obtain error-free computation from such fabrics
                 containing defective elements.\par

                 In this article, an application-independent defect
                 tolerant scheme for reconfigurable crossbar array
                 nanoarchitectures is presented. The main feature of
                 this approach is that the existence and location of
                 defective resources within the nano-fabric are hidden
                 from the entire design flow, resulting in minimum
                 post-fabrication customization per chip and minimum
                 changes to the entire design and synthesis flow. It is
                 also shown how to drastically minimize the area
                 overhead associated with this flow. The proposed
                 technique requires extraction of regular yet incomplete
                 defect-free subsets, in contrast to previously proposed
                 complete defect-free subsets. This can greatly reduce
                 the area overhead required for defect tolerance while
                 not sacrificing logic mapping or signal routing
                 capabilities. Extensive simulation results confirm
                 considerable reduction in the area overhead without any
                 negative impact on the usability of modified
                 defect-free subsets.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Defect tolerance; nanotechnology; reconfigurable
                 architectures",
}

@Article{Chakraborty:2009:SAD,
  author =       "Rajat Subhra Chakraborty and Swarup Bhunia",
  title =        "A study of asynchronous design methodology for robust
                 {CMOS}-nano hybrid system design",
  journal =      j-JETC,
  volume =       "5",
  number =       "3",
  pages =        "12:1--12:??",
  month =        aug,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1568485.1568486",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:41 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Among the emerging alternatives to CMOS, molecular
                 electronics based diode-resistor crossbar fabric has
                 generated considerable interest in recent times. Logic
                 circuit design with future nano-scale molecular devices
                 using dense and regular crossbar fabrics is promising
                 in terms of integration density, performance and power
                 dissipation. However, circuit design using molecular
                 switches involve some major challenges: (1) lack of
                 voltage gain of these switches that prevents logic
                 cascading; (2) large output voltage level degradation;
                 (3) vulnerability to parameter variations that affect
                 yield and robustness of operation; and (4) high defect
                 rate. In this article, we analyze some of the above
                 challenges and investigate the effectiveness of
                 asynchronous design methodology in a hybrid system
                 design platform using molecular crossbar and CMOS
                 interfacing elements. We explore different approaches
                 of asynchronous circuit design and compare their
                 suitability in terms of several circuit design
                 parameters. We then develop the methodology and an
                 automated synthesis flow to support two different
                 asynchronous design approaches ({\em Micropipelines\/}
                 and {\em Four phase Dual-rail\/}) for system designs
                 using nano-crossbar logic stages and CMOS interface
                 data-storage elements. Circuit-level simulation results
                 for several benchmarks show considerable advantage in
                 terms of performance and robustness at moderate area
                 and power overhead compared to two different
                 synchronous implementations.",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Asynchronous design; CMOS-nano co-design; dual-rail
                 circuits; logic degradation; micropipelines; nano-scale
                 crossbar; robust design",
}

@Article{Zhang:2009:HNCa,
  author =       "Wei Zhang and Niraj K. Jha and Li Shang",
  title =        "A hybrid {Nano\slash CMOS} dynamically reconfigurable
                 system --- {Part II}: {Design} optimization flow",
  journal =      j-JETC,
  volume =       "5",
  number =       "3",
  pages =        "13:1--13:??",
  month =        aug,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1568485.1568487",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:41 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In Part I of this work, a hybrid nano/CMOS
                 reconfigurable architecture, called NATURE, was
                 described. It is composed of CMOS reconfigurable logic
                 and interconnect fabric, and nonvolatile nano on-chip
                 memory. Through its support for cycle-by-cycle runtime
                 reconfiguration and a highly-efficient computation
                 model, temporal logic folding, NATURE improves logic
                 density and area-delay product by more than an order of
                 magnitude compared to existing CMOS-based
                 field-programmable gate arrays (FPGAs). NATURE can be
                 fabricated using mainstream photo-lithography
                 fabrication techniques. Thus, it offers a currently
                 commercially feasible architecture with high
                 performance, superior logic density, and excellent
                 runtime design flexibility.\par

                 In Part II of this work, we present an integrated
                 design and optimization flow for NATURE, called
                 NanoMap. Given an input design specified in
                 register-transfer level (RTL) and/or gate-level VHDL,
                 NanoMap optimizes and implements the design on NATURE
                 through logic mapping, temporal clustering, temporal
                 placement, and routing. As opposed to other design
                 tools for traditional FPGAs, NanoMap supports and
                 leverages temporal logic folding by integrating novel
                 mapping techniques. It can automatically explore and
                 identify the best temporal logic folding configuration,
                 targeting area, delay or area-delay product
                 optimization. A force-directed scheduling technique is
                 used to optimize and balance resource usage across
                 different folding cycles. By supporting logic folding,
                 NanoMap can provide significant design flexibility in
                 performing area-delay trade-offs under various
                 user-specified constraints. We present details of the
                 mapping procedure and results for different
                 architectural instances. Experimental results
                 demonstrate that NanoMap can judiciously trade off area
                 and delay targeting different optimization goals, and
                 effectively exploit the advantages of NATURE.\par

                 Part I of this work will appear in JETC Vol. 5, No.
                 4.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "design optimization flow; Dynamic reconfiguration;
                 logic folding; NATURE",
}

@Article{Simsir:2009:HNC,
  author =       "Muzaffer O. Simsir and Srihari Cadambi and Franjo
                 Ivanv{\v{c}}i{\'c} and Martin Roetteler and Niraj
                 K. Jha",
  title =        "A hybrid nano-{CMOS} architecture for defect and fault
                 tolerance",
  journal =      j-JETC,
  volume =       "5",
  number =       "3",
  pages =        "14:1--14:??",
  month =        aug,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1568485.1568488",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:41 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "As the end of the semiconductor roadmap for CMOS
                 approaches, architectures based on nanoscale molecular
                 devices are attracting attention. Among several
                 alternatives, silicon nanowires and carbon nanotubes
                 are the two most promising nanotechnologies according
                 to the ITRS. These technologies may enable scaling deep
                 into the nanometer regime. However, they suffer from
                 very defect-prone manufacturing processes. Although the
                 reconfigurability property of the nanoscale devices can
                 be used to tolerate high defect rates, it may not be
                 possible to locate all defects. With very high device
                 densities, testing each component may not be possible
                 because of time or technology restrictions. This points
                 to a scenario in which even though the devices are
                 tested, the tests are not very comprehensive at
                 locating defects, and hence the shipped chips are still
                 defective. Moreover, the devices in the nanometer range
                 will be susceptible to transient faults which can
                 produce arbitrary soft errors. Despite these drawbacks,
                 it is possible to make nanoscale architectures
                 practical and realistic by introducing defect and fault
                 tolerance. In this article, we propose and evaluate a
                 hybrid nanowire-CMOS architecture that addresses all
                 three problems --- namely high defect rates, unlocated
                 defects, and transient faults --- at the same time.
                 This goal is achieved by using multiple levels of
                 redundancy and majority voters. A key aspect of the
                 architecture is that it contains a judicious balance of
                 both nanoscale and traditional CMOS components. A
                 companion to the architecture is a compiler with
                 heuristics to quickly determine if logic can be mapped
                 onto partially defective nanoscale elements. The
                 heuristics make it possible to introduce
                 defect-awareness in placement and routing. The
                 architecture and compiler are evaluated by applying the
                 complete design flow to several benchmarks.",
  acknowledgement = ack-nhfb,
  articleno =    "14",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Defect tolerance; nanotechnology; nanowires",
}

@Article{Wang:2009:UQD,
  author =       "Shuo Wang and Jianwei Dai and El-Sayed Hasaneen and
                 Lei Wang and Faquir Jain",
  title =        "Utilizing quantum dot transistors with programmable
                 threshold voltages for low-power mobile computing",
  journal =      j-JETC,
  volume =       "5",
  number =       "3",
  pages =        "15:1--15:??",
  month =        aug,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1568485.1568489",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:41 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Power consumption poses one of the fundamental
                 barriers for deploying mobile computing devices in
                 energy-constrained situations with varying operation
                 conditions. In particular, leakage power is projected
                 to increase exponentially in future semiconductor
                 process nodes. This challenging problem is pressing for
                 renewed focus on power-performance optimization at all
                 levels of design abstract, from novel device structures
                 to fundamental shifts in design paradigm. In this
                 article, we propose to exploit the programmable
                 threshold voltage quantum dot (QD) transistors to
                 reduce leakage thereby improving the energy efficiency
                 for mobile computing. The unique programmability and
                 reconfigurability enabled by QD transistors extend our
                 capability in design optimization for new
                 power-performance trade-offs. Simulation results
                 demonstrate the significant leakage reduction over
                 conventional techniques.",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Low power; threshold voltage and quantum dot
                 transistor",
}

@Article{Zhang:2009:HNCb,
  author =       "Wei Zhang and Niraj K. Jha and Li Shang",
  title =        "A hybrid {nano\slash CMOS} dynamically reconfigurable
                 system --- {Part I}: {Architecture}",
  journal =      j-JETC,
  volume =       "5",
  number =       "4",
  pages =        "16:1--16:??",
  month =        nov,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1629091.1629092",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Rapid progress on nanodevices points to a promising
                 direction for future circuit design. However, since
                 nanofabrication techniques are not yet mature,
                 implementation of nanocircuits, at least on a large
                 scale, in the near future is infeasible. To ease
                 fabrication and overcome the problem of high defect
                 levels in nanotechnology, hybrid nano/CMOS
                 reconfigurable architectures are attractive choices.
                 Moreover, if the current photolithography fabrication
                 process can be used to manufacture the hybrid chips,
                 the benefits of nanotechnologies can be realized
                 today.\par

                 Traditional reconfigurable architectures can only
                 support partial or coarse-grain runtime reconfiguration
                 due to their limited on-chip storage and long off-chip
                 reconfiguration latency. Recent progress on nano Random
                 Access Memories (RAMs), such as carbon nanotube-based
                 RAM (NRAM), Phase-Change Memory (PCM), magnetoresistive
                 RAM (MRAM), etc., provides us with a chance to realize
                 on-chip fine-grain runtime reconfiguration. These nano
                 RAMs have good compatibility with the current
                 fabrication process. By utilizing them in the hybrid
                 design, we can take advantage of both CMOS and
                 nanotechnology, and greatly improve the logic density,
                 resource utilization, and performance of our
                 design.\par

                 In this article, we propose a high-performance
                 reconfigurable architecture, called NATURE, that
                 utilizes CMOS logic and nano RAMs. An automatic design
                 flow for NATURE is presented in Part II of the article.
                 In NATURE, the highly dense nonvolatile nano RAMs are
                 distributed throughout the chip to allow large embedded
                 on-chip configuration storage, which enables fast
                 reading and hence supports fine-grain runtime
                 reconfiguration and temporal logic folding of a circuit
                 before being mapped to the architecture. Temporal logic
                 folding can significantly increase the logic density of
                 NATURE (by over an order of magnitude for large
                 circuits) while remaining competitive in performance
                 and power consumption. For ease of exposition, we use
                 NRAMs to illustrate various concepts in this article
                 due to the excellent properties of NRAMs. However,
                 other nano RAMs can also be used instead. Experimental
                 results based on NRAMs establish the efficacy of
                 NATURE.",
  acknowledgement = ack-nhfb,
  articleno =    "16",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "logic folding; NRAM; runtime reconfiguration",
}

@Article{Zhang:2009:DSE,
  author =       "Wei Zhang and Niraj K. Jha and Li Shang",
  title =        "Design space exploration and data memory architecture
                 design for a hybrid {nano\slash CMOS} dynamically
                 reconfigurable architecture",
  journal =      j-JETC,
  volume =       "5",
  number =       "4",
  pages =        "17:1--17:??",
  month =        nov,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1629091.1629093",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In recent years, research on nanotechnology has
                 advanced rapidly. Novel nanodevices have been
                 developed, such as those based on carbon nanotubes,
                 nanowires, etc. Using these emerging nanodevices,
                 diverse nanoarchitectures have been proposed. Among
                 them, hybrid nano/CMOS reconfigurable architectures
                 have attracted attention because of their advantages in
                 performance, integration density, and fault tolerance.
                 Recently, a high-performance hybrid nano/CMOS
                 reconfigurable architecture, called NATURE, was
                 presented. NATURE comprises CMOS reconfigurable logic
                 and interconnect fabric, and
                 CMOS-fabrication-compatible nanomemory. High-density,
                 fast nano RAMs are distributed in NATURE as on-chip
                 storage to store multiple reconfiguration copies for
                 each reconfigurable element. It enables cycle-by-cycle
                 runtime reconfiguration and a highly efficient
                 computational model, called temporal logic folding.
                 Through logic folding, NATURE provides more than an
                 order of magnitude improvement in logic density and
                 area-delay product, and significant design flexibility
                 in performing area-delay trade-offs, at the same
                 technology node. Moreover, NATURE can be fabricated
                 using mainstream photolithography fabrication
                 techniques. Hence, it offers a currently commercially
                 viable reconfigurable architecture with high
                 performance, superior logic density, and outstanding
                 design flexibility, which is very attractive for
                 deployment in cost-conscious embedded systems.\par

                 In order to fully explore the potential of NATURE and
                 further improve its performance, in this article, a
                 thorough design space exploration is conducted to
                 optimize its architecture. Investigations in terms of
                 different logic element architectures, interconnect
                 designs, and various technologies for nano RAMs are
                 presented. Nano RAMs can not only be used as storage
                 for configuration bits, but the high density of nano
                 RAMs also makes them excellent candidates for
                 large-capacity on-chip data storage in NATURE. Many
                 logic- and memory-intensive applications, such as video
                 and image processing, require large storage of temporal
                 results. To enhance the capability of NATURE for
                 implementing such applications, we investigate the
                 design of nano data memory structures in NATURE and
                 explore the impact of memory density. Experimental
                 results demonstrate significant throughput improvements
                 due to area saving from logic folding and parallel data
                 processing.",
  acknowledgement = ack-nhfb,
  articleno =    "17",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "logic folding; Nano data RAM; runtime
                 reconfiguration",
}

@Article{Tang:2009:DET,
  author =       "Weiguo Tang and Lei Wang and Fabrizio Lombardi",
  title =        "A defect\slash error-tolerant nanosystem architecture
                 for {DSP}",
  journal =      j-JETC,
  volume =       "5",
  number =       "4",
  pages =        "18:1--18:??",
  month =        nov,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1629091.1629094",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Emerging technologies such as silicon NanoWires (NW)
                 and Carbon NanoTubes (CNT) have shown great potential
                 for building the next generation of computing systems
                 in the nano ranges. However, the excessive number of
                 defects originating from bottom-up fabrication (such as
                 a self-assembly process) poses a pressing challenge for
                 achieving scalable system integration. This article
                 proposes a new nanosystem architecture that employs
                 nanowire crossbars for Digital Signal Processing (DSP)
                 applications. Distributed arithmetic is utilized such
                 that complex signal processing computation can be
                 mapped into regular memory operations, thus making this
                 architecture well suited for implementation by nanowire
                 crossbars. Furthermore, the inherent features of
                 DSP-type computation provide new insights to remedy
                 errors (as logic/computational manifestation of
                 defects). A new defect/error-tolerant technique that
                 exploits algorithmic error compensation is proposed; at
                 system level different trade-offs between correctness
                 in output and performance are established while
                 retaining low overhead in its implementation. As an
                 instance of its application, the proposed approach has
                 been utilized to a generic DSP nanosystem performing
                 frequency-selective filtering. Simulation results show
                 that the proposed nanoDSP introduces only a minor
                 performance degradation under high defect rates and at
                 a range of operational conditions. The proposed
                 technique also features good scalability and viability
                 for various DSP applications.",
  acknowledgement = ack-nhfb,
  articleno =    "18",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "algorithmic error compensation; Distributed
                 arithmetic; DSP nanosystem; inner product",
}

@Article{Dysart:2009:OWR,
  author =       "Timothy J. Dysart and Peter M. Kogge",
  title =        "Organizing wires for reliability in magnetic {QCA}",
  journal =      j-JETC,
  volume =       "5",
  number =       "4",
  pages =        "19:1--19:??",
  month =        nov,
  year =         "2009",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1629091.1629095",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:23:55 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "This article investigates, via analytic modeling, how
                 a magnetic QCA wire should be organized to provide the
                 highest reliability. We compare a nonredundant wire and
                 two redundant wire organizations. For all three
                 organizations, a fault rate per unit length is used for
                 comparison; additionally, since extra components are
                 necessary to implement the redundant organizations,
                 these components are faulty as well. We show that the
                 difference between these two fault rates is the main
                 driver for selecting a wire organization. Lastly, we
                 develop a guideline for selecting the most reliable
                 wire organization during the circuit design process.",
  acknowledgement = ack-nhfb,
  articleno =    "19",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "modular redundancy; nanomagnet logic; QCA",
}

@Article{Chakrabarty:2010:E,
  author =       "Krishnendu Chakrabarty",
  title =        "Editorial",
  journal =      j-JETC,
  volume =       "6",
  number =       "1",
  pages =        "1:1--1:??",
  month =        mar,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1721650.1721651",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:24:05 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Lee:2010:FBP,
  author =       "Chun-Yi Lee and Niraj K. Jha",
  title =        "{FinFET}-based power simulator for interconnection
                 networks",
  journal =      j-JETC,
  volume =       "6",
  number =       "1",
  pages =        "2:1--2:??",
  month =        mar,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1721650.1721652",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:24:05 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Double-gate FETs, specifically FinFETs, are emerging
                 as promising substitutes for bulk CMOS at the 32nm
                 technology node and beyond because of the various
                 obstacles to scaling faced by CMOS, such as
                 short-channel effects, leakage power, and process
                 variations. Another trend in chip multiprocessor design
                 is incorporation of sophisticated on-chip
                 interconnection networks. However, such networks are
                 significant power-consumers. In this article, we
                 address these two trends by presenting a power
                 simulator for FinFET-based on-chip interconnection
                 networks. It estimates both dynamic and leakage power.
                 We present results for various FinFET design styles and
                 temperatures (since leakage power changes drastically
                 with temperature), and show that one FinFET design
                 style may be much superior to another from the power
                 consumption point of view.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "FinFETs; interconnection network; power consumption;
                 power simulator",
}

@Article{Liu:2010:RSO,
  author =       "Yang Liu and Chris Dwyer and Alvin R. Lebeck",
  title =        "Routing in self-organizing nano-scale irregular
                 networks",
  journal =      j-JETC,
  volume =       "6",
  number =       "1",
  pages =        "3:1--3:??",
  month =        mar,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1721650.1721653",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Mar 17 14:24:05 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The integration of novel nanotechnologies onto silicon
                 platforms is likely to increase fabrication defects
                 compared with traditional CMOS technologies.
                 Furthermore, the number of nodes connected with these
                 networks makes acquiring a global defect map
                 impractical. As a result, on-chip networks will provide
                 defect tolerance by self-organizing into irregular
                 topologies. In this scenario, simple static routing
                 algorithms based on regular physical topologies, such
                 as meshes, will be inadequate. Additionally, previous
                 routing approaches for irregular networks assume
                 abundant resources and do not apply to this domain of
                 resource-constrained self-organizing nano-scale
                 networks. Consequently, routing algorithms that work in
                 irregular networks with limited resources are
                 needed.\par

                 In this article, we explore routing for self-organizing
                 nano-scale irregular networks in the context of a
                 Self-Organizing SIMD Architecture (SOSA). Our approach
                 trades configuration time and a small amount of storage
                 for reduced communication latency. We augment an Euler
                 path-based routing technique for trees to generate
                 static shortest paths between certain pairs of nodes
                 while remaining deadlock free. Simulations of several
                 applications executing on SOSA show our proposed
                 routing algorithm can reduce execution time by 8\% to
                 30\%.",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "data parallel; DNA; nanocomputing; Self-organizing;
                 SIMD",
}

@Article{Kocak:2010:IDT,
  author =       "Taskin Kocak and Dhiraj Pradhan",
  title =        "Introduction to design techniques for energy
                 harvesting",
  journal =      j-JETC,
  volume =       "6",
  number =       "2",
  pages =        "4:1--4:??",
  month =        jun,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1773814.1773815",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Sep 7 08:33:18 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Wenck:2010:SST,
  author =       "Justin Wenck and Jamie Collier and Jeff Siebert and
                 Rajeevan Amirtharajah",
  title =        "Scaling self-timed systems powered by mechanical
                 vibration energy harvesting",
  journal =      j-JETC,
  volume =       "6",
  number =       "2",
  pages =        "5:1--5:??",
  month =        jun,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1773814.1773816",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Sep 7 08:33:18 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Passive energy harvesting from mechanical vibration
                 has wide application in wearable devices and wireless
                 sensors to complement or replace batteries. Energy
                 harvesting efficiency can be increased by eliminating
                 AC/DC conversion. A test chip demonstrating
                 self-timing, power-on reset circuitry, and dynamic
                 memory for energy harvesting AC voltages has been
                 designed in 180 nm CMOS and tested. An energy scalable
                 DSP architecture implements FIR filters that consume as
                 little as 170 pJ per output sample. The on-chip DRAM
                 retains data for up to 28 ms while register data is
                 retained down to a supply voltage of 153 mV. Circuit
                 operation is confirmed for supply frequencies between
                 60 Hz and 1 kHz with power consumption below 130$\mu$W.
                 Reaching the limits of miniaturization will require
                 approaching the limits of power dissipation. We
                 extrapolate from this DSP architecture to find the
                 minimum volume required for mechanical vibration energy
                 harvesting sensors.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "AC power supply; DRAM; energy-aware systems; energy
                 harvesting; integrated circuits; low-power design;
                 power-on reset; scaling; self-timed",
}

@Article{Wang:2010:DCS,
  author =       "W. S. Wang and T. O'Donnell and N. Wang and M. Hayes
                 and B. O'Flynn and C. O'Mathuna",
  title =        "Design considerations of sub-{mW} indoor light energy
                 harvesting for wireless sensor systems",
  journal =      j-JETC,
  volume =       "6",
  number =       "2",
  pages =        "6:1--6:??",
  month =        jun,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1773814.1773817",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Sep 7 08:33:18 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "For most wireless sensor networks, one common and
                 major bottleneck is the limited battery lifetime. The
                 frequent maintenance efforts associated with battery
                 replacement significantly increase the system
                 operational and logistics cost. Unnoticed power
                 failures on nodes will degrade the system reliability
                 and may lead to system failure. In building management
                 applications, to solve this problem, small energy
                 sources such as indoor light energy are promising to
                 provide long-term power to these distributed wireless
                 sensor nodes. This article provides comprehensive
                 design considerations for an indoor light energy
                 harvesting system for building management applications.
                 Photovoltaic cells characteristics, energy storage
                 units, power management circuit design, and power
                 consumption pattern of the target mote are presented.
                 Maximum power point tracking circuits are proposed
                 which significantly increase the power obtained from
                 the solar cells. The novel fast charge circuit reduces
                 the charging time. A prototype was then successfully
                 built and tested in various indoor light conditions to
                 discover the practical issues of the design. The
                 evaluation results show that the proposed prototype
                 increases the power harvested from the PV cells by 30\%
                 and also accelerates the charging rate by 34\% in a
                 typical indoor lighting condition. By entirely
                 eliminating the rechargeable battery as energy storage,
                 the proposed system would expect an operational
                 lifetime 10--20 years instead of the current less than
                 6 months battery lifetime.",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Design consideration; energy harvesting; indoor light
                 illuminance; maximum power point tracking; PV cells
                 wireless sensor node; supercapacitor",
}

@Article{Moser:2010:EMF,
  author =       "Clemens Moser and Jian-Jia Chen and Lothar Thiele",
  title =        "An energy management framework for energy harvesting
                 embedded systems",
  journal =      j-JETC,
  volume =       "6",
  number =       "2",
  pages =        "7:1--7:??",
  month =        jun,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1773814.1773818",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Sep 7 08:33:18 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Energy harvesting (also known as energy scavenging) is
                 the process of generating electrical energy from
                 environmental energy sources. There exists a variety of
                 different energy sources such as solar energy, kinetic
                 energy, or thermal energy. In recent years, this term
                 has been frequently applied in the context of small
                 autonomous devices such as wireless sensor nodes. In
                 this article, a framework for energy management in
                 energy harvesting embedded systems is presented. As a
                 possible scenario, we focus on wireless sensor nodes
                 that are powered by solar cells. We demonstrate that
                 classical power management solutions have to be
                 reconceived and/or new problems arise if perpetual
                 operation of the system is required. In particular, we
                 provide a set of algorithms and methods for various
                 application scenarios, including real-time scheduling,
                 application rate control, as well as reward
                 maximization. The goal is to optimize the performance
                 of the application subject to given energy constraints.
                 Our methods optimize the system performance which, for
                 example, allows the usage of smaller solar cells and
                 smaller batteries. Furthermore, we show how to
                 dimension important system parameters like the minimum
                 battery capacity or a sufficient prediction horizon.
                 Our theoretical results are supported by simulations
                 using long-term measurements of solar energy in an
                 outdoor environment. In contrast to previous works, we
                 present a formal framework which is able to capture the
                 performance, the parameters, and the energy model of
                 various energy harvesting systems. We combine different
                 viewpoints, include corresponding simulation results,
                 and provide a thorough discussion of implementation
                 aspects.",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "embedded systems; energy harvesting; model predictive
                 control; Power management; real-time scheduling; reward
                 maximization",
}

@Article{Mohanty:2010:UDS,
  author =       "Saraju P. Mohanty and Dhiraj K. Pradhan",
  title =        "{ULS}: {A} dual-{$V_{th}$} \slash high-$\kappa$
                 nano-{CMOS} universal level shifter for system-level
                 power management",
  journal =      j-JETC,
  volume =       "6",
  number =       "2",
  pages =        "8:1--8:??",
  month =        jun,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1773814.1773819",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Sep 7 08:33:18 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Power dissipation is a major bottleneck for emerging
                 applications, such as implantable systems, digital
                 cameras, and multimedia processors. Each of these
                 applications is essentially designed as an
                 Analog/Mixed-Signal System-on-a-Chip (AMS-SoC). These
                 AMS-SoCs are typically operated from a single
                 power-supply source which is a battery providing a
                 constant supply voltage. In order to reduce power
                 dissipation of the AMS-SoCs, multiple-supply voltage
                 and/or variable-supply voltage is used as an attractive
                 low-power design approach. In the
                 multiple-/variable-supply voltage AMS-SoCs the use of a
                 DC-to-DC voltage-level shifter is critical. The
                 voltage-level shifter is an overhead when its own power
                 dissipation is high. In this article a new DC-to-DC
                 voltage-level shifter is introduced that performs
                 level-up shifting, level-down shifting, and blocking of
                 voltages and is called Universal Level Shifter (ULS).
                 The ULS is a unique component that reduces dynamic
                 power and leakage of the AMS-SoCs while facilitating
                 their reconfigurability. The system-level architectures
                 for three AMS-SoCs, such as Drug Delivery
                 Nano-Electro-Mechanical-System (DDNEMS), Secure Digital
                 Camera (SDC), and Net-centric Multimedia Processor
                 (NMP) are introduced to demonstrate the use the ULS for
                 system-level power management. The article presents a
                 design flow and an algorithm for optimal design of the
                 ULS using a dual- $V_{th}$ high-$\kappa$ technique for
                 efficient realization of ULS. A prototype ULS is
                 presented for 32nm nano-CMOS technology node. The
                 robustness of the ULS design is examined by performing
                 three types of analysis, such as parametric, load, and
                 power. It is observed that the ULS produces a stable
                 output for voltages as low as 0.35 V and loads varying
                 from 50 {\em fF\/} to 120 {\em fF}. The average power
                 dissipation of the ULS with a 82 {\em fF\/} capacitive
                 load is 5 $\mu${\em W}.",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "Analog/Mixed-Signal System-on-a-Chip (AMS-SoC);
                 DC-to-DC voltage-level shifter; dual-threshold voltage;
                 high-\kappa low-power design; /metal-gate nano-CMOS;
                 nanoscale CMOS; Power management; system-level power
                 management",
}

@Article{Dai:2010:ITA,
  author =       "Jianwei Dai and Lei Wang and Fabrizio Lombardi",
  title =        "An information-theoretic analysis of quantum-dot
                 cellular automata for defect tolerance",
  journal =      j-JETC,
  volume =       "6",
  number =       "3",
  pages =        "9:1--9:??",
  month =        aug,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1777401.1777402",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Sep 7 08:33:31 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Quantum-dot cellular automata (QCA) has been advocated
                 as a promising emerging nanotechnology for designing
                 future nanocomputing systems. However, at device level,
                 the large number of expected defects represents a
                 significant hurdle for reliable computation in
                 QCA-based systems. In this paper, we present an
                 information-theoretic approach to investigate the
                 relationship between defect tolerance and redundancy in
                 QCA devices. By modeling defect-prone QCA devices as
                 unreliable information processing media, we determine
                 the information transfer capacity, as bound on the
                 reliability that QCA devices can achieve. The proposed
                 method allows to evaluate the effectiveness of
                 redundancy-based defect tolerance in an effective and
                 quantitative manner.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "defect tolerance; information theoretic analysis; QCA;
                 reliability",
}

@Article{Zhang:2010:LPN,
  author =       "Wei Zhang and Niraj K. Jha and Li Shang",
  title =        "Low-power {$3$D} nano\slash {CMOS} hybrid dynamically
                 reconfigurable architecture",
  journal =      j-JETC,
  volume =       "6",
  number =       "3",
  pages =        "10:1--10:??",
  month =        aug,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1777401.1777403",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Sep 7 08:33:31 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In order to continue technology scaling beyond CMOS,
                 diverse nanoarchitectures have been proposed in recent
                 years based on emerging nanodevices, such as nanotubes,
                 nanowires, etc. Among them, some hybrid nano/CMOS
                 reconfigurable architectures enjoy the advantage that
                 they can be fabricated using photolithography. NATURE
                 is one such architecture that we have proposed
                 recently. It comprises CMOS reconfigurable logic and
                 CMOS fabrication-compatible nano RAMs. It uses
                 distributed high-density and fast nano RAMs as on-chip
                 storage for storing multiple reconfiguration copies,
                 enabling fine-grain cycle-by-cycle reconfiguration. It
                 supports a highly efficient computational model, called
                 temporal logic folding, which makes possible more than
                 an order of magnitude improvement in logic density and
                 area-delay product, significant power reduction, and
                 significant design flexibility in performing area-delay
                 trade-offs.\par

                 In this article, we extend NATURE in various
                 dimensions, evaluating various FPGA approaches in the
                 context of today's emerging technologies. First, we
                 explore the introduction of embedded coarse-grain
                 modules in the fine-grain NATURE architecture and
                 present a unified dynamically reconfigurable
                 architecture, which can significantly enhance NATURE's
                 computation power for data-dominated applications.
                 Second, we explore a 3D architecture for NATURE in
                 which the nano RAM for reconfiguration storage is on
                 one layer and the rest of the CMOS logic on another
                 layer. This leads to further improvements in logic
                 density and performance. Finally, we explore the
                 possibility of using FinFETs, an emerging double-gate
                 CMOS technology, to implement NATURE. Since power
                 consumption is an important consideration in the deep
                 nanometer regime, especially for FPGAs, we present a
                 back-gate biasing methodology for flexible threshold
                 voltage adjustment in FinFETs to significantly reduce
                 NATURE's power consumption. Simulation results
                 demonstrate the efficacy of the proposed methods.",
  acknowledgement = ack-nhfb,
  articleno =    "10",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "3D design; Coarse-grain; FinFET; runtime
                 reconfiguration",
}

@Article{Zhao:2010:ICP,
  author =       "Yang Zhao and Tao Xu and Krishnendu Chakrabarty",
  title =        "Integrated control-path design and error recovery in
                 the synthesis of digital microfluidic lab-on-chip",
  journal =      j-JETC,
  volume =       "6",
  number =       "3",
  pages =        "11:1--11:??",
  month =        aug,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://doi.acm.org/10.1145/1777401.1777404",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Sep 7 08:33:31 MDT 2010",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Recent advances in digital microfluidics have led to
                 tremendous interest in miniaturized lab-on-chip devices
                 for biochemical analysis. Synthesis tools have also
                 emerged for the automated design of lab-on-chip from
                 the specifications of laboratory protocols. However,
                 none of these tools consider control flow or address
                 the problem of recovering from fluidic errors that can
                 occur during on-chip bioassay execution. We present a
                 synthesis method that incorporates control paths and an
                 error-recovery mechanism in the design of a digital
                 microfluidic lab-on-chip. Based on error-propagation
                 estimates, we determine the best locations for fluidic
                 checkpoints during biochip synthesis. A microcontroller
                 coordinates the implementation of the
                 control-flow-based bioassay by intercepting the
                 synthesis results that are mapped to the software
                 programs. Real-life bioassay applications are used as
                 case studies to evaluate the proposed design method.
                 For a representative protein assay, compared to a
                 baseline chip design, the biochip with a control path
                 can reduce the completion time by 30\% when errors
                 occur during the implementation of the bioassay.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
  keywords =     "biochips; Error recovery; microfluidics; synthesis",
}

@Article{Bhoj:2010:GDF,
  author =       "Ajay N. Bhoj and Niraj K. Jha",
  title =        "Gated-diode {FinFET DRAMs}: Device and circuit
                 design-considerations",
  journal =      j-JETC,
  volume =       "6",
  number =       "4",
  pages =        "12:1--12:??",
  month =        dec,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1877745.1877746",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Mar 28 12:17:02 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Saeedi:2010:RCS,
  author =       "Mehdi Saeedi and Morteza Saheb Zamani and Mehdi
                 Sedighi and Zahra Sasanian",
  title =        "Reversible circuit synthesis using a cycle-based
                 approach",
  journal =      j-JETC,
  volume =       "6",
  number =       "4",
  pages =        "13:1--13:??",
  month =        dec,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1877745.1877747",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Mar 28 12:17:02 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Thapliyal:2010:DRS,
  author =       "Himanshu Thapliyal and Nagarajan Ranganathan",
  title =        "Design of reversible sequential circuits optimizing
                 quantum cost, delay, and garbage outputs",
  journal =      j-JETC,
  volume =       "6",
  number =       "4",
  pages =        "14:1--14:??",
  month =        dec,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1877745.1877748",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Mar 28 12:17:02 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "14",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Singh:2010:CPD,
  author =       "Montek Singh and Steven M. Nowick",
  title =        "Call for Papers: Deadline: {March 15, 2011}",
  journal =      j-JETC,
  volume =       "6",
  number =       "4",
  pages =        "15:1--15:??",
  month =        dec,
  year =         "2010",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1877745.1877749",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Mar 28 12:17:02 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Das:2011:ISI,
  author =       "Shamik Das and Garrett S. Rose",
  title =        "Introduction to Special Issue: Highlights of
                 {NANOARCH'09}",
  journal =      j-JETC,
  volume =       "7",
  number =       "1",
  pages =        "1:1--1:??",
  month =        jan,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1899390.1899391",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Mar 28 12:17:03 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Dingler:2011:PEI,
  author =       "Aaron Dingler and Michael T. Niemier and Xiaobo Sharon
                 Hu and Evan Lent",
  title =        "Performance and Energy Impact of Locally Controlled
                 {NML} Circuits",
  journal =      j-JETC,
  volume =       "7",
  number =       "1",
  pages =        "2:1--2:??",
  month =        jan,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1899390.1899392",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Mar 28 12:17:03 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Gaillardon:2011:MNB,
  author =       "P.-E. Gaillardon and F. Clermidy and I. O'Connor and
                 J. Liu and M. Amadou and G. Nicolescu",
  title =        "Matrix Nanodevice-Based Logic Architectures and
                 Associated Functional Mapping Method",
  journal =      j-JETC,
  volume =       "7",
  number =       "1",
  pages =        "3:1--3:??",
  month =        jan,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1899390.1899393",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Mar 28 12:17:03 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Haron:2011:RRN,
  author =       "Nor Zaidi Haron and Said Hamdioui",
  title =        "Redundant Residue Number System Code for
                 Fault-Tolerant Hybrid Memories",
  journal =      j-JETC,
  volume =       "7",
  number =       "1",
  pages =        "4:1--4:??",
  month =        jan,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1899390.1899394",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Mar 28 12:17:03 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Shang:2011:INC,
  author =       "Li Shang and Qianfan Xu",
  title =        "Introduction to nanophotonic communication technology
                 integration",
  journal =      j-JETC,
  volume =       "7",
  number =       "2",
  pages =        "5:1--5:??",
  month =        jun,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1970406.1970407",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Aug 18 12:25:12 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Beausoleil:2011:LSI,
  author =       "Raymond G. Beausoleil",
  title =        "Large-scale integrated photonics for high-performance
                 interconnects",
  journal =      j-JETC,
  volume =       "7",
  number =       "2",
  pages =        "6:1--6:??",
  month =        jun,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1970406.1970408",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Aug 18 12:25:12 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Biberman:2011:PNC,
  author =       "Aleksandr Biberman and Kyle Preston and Gilbert Hendry
                 and Nicol{\'a}s Sherwood-Droz and Johnnie Chan and
                 Jacob S. Levy and Michal Lipson and Keren Bergman",
  title =        "Photonic network-on-chip architectures using
                 multilayer deposited silicon materials for
                 high-performance chip multiprocessors",
  journal =      j-JETC,
  volume =       "7",
  number =       "2",
  pages =        "7:1--7:??",
  month =        jun,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1970406.1970409",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Aug 18 12:25:12 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Li:2011:IHN,
  author =       "Zheng Li and Moustafa Mohamed and Xi Chen and Hongyu
                 Zhou and Alan Mickelson and Li Shang and Manish
                 Vachharajani",
  title =        "{Iris}: {A} hybrid nanophotonic network design for
                 high-performance and low-power on-chip communication",
  journal =      j-JETC,
  volume =       "7",
  number =       "2",
  pages =        "8:1--8:??",
  month =        jun,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1970406.1970410",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Aug 18 12:25:12 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Cianchetti:2011:LLH,
  author =       "Mark J. Cianchetti and David H. Albonesi",
  title =        "A low-latency, high-throughput on-chip optical router
                 architecture for future chip multiprocessors",
  journal =      j-JETC,
  volume =       "7",
  number =       "2",
  pages =        "9:1--9:??",
  month =        jun,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/1970406.1970411",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Aug 18 12:25:12 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Zhang:2011:FBP,
  author =       "Meng Zhang and Niraj K. Jha",
  title =        "{FinFET}-Based Power Management for Improved {DPA}
                 Resistance with Low Overhead",
  journal =      j-JETC,
  volume =       "7",
  number =       "3",
  pages =        "10:1--10:??",
  month =        aug,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2000502.2000503",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Aug 18 12:25:13 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Differential power analysis (DPA) is a side-channel
                 attack that statistically analyzes the power
                 consumption of a cryptographic system to obtain secret
                 information. This type of attack is well known as a
                 major threat to information security. Effective
                 solutions with low energy and area cost for improved
                 DPA resistance are urgently needed, especially for
                 energy-constrained modern devices that are often in the
                 physical proximity of attackers. This article presents
                 a novel countermeasure against DPA attacks on smart
                 cards and other digital ICs based on FinFETs, an
                 emerging substitute for bulk CMOS at the 22nm
                 technology node and beyond. We exploit the adaptive
                 power management characteristic of FinFETs to generate
                 a high level of noise at critical moments in the
                 execution of a cryptosystem to thwart DPA attacks.",
  acknowledgement = ack-nhfb,
  articleno =    "10",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Choi:2011:EQI,
  author =       "Byung-Soo Choi and Rodney {Van Meter}",
  title =        "On the Effect of Quantum Interaction Distance on
                 Quantum Addition Circuits",
  journal =      j-JETC,
  volume =       "7",
  number =       "3",
  pages =        "11:1--11:17",
  month =        aug,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2000502.2000504",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Aug 18 12:25:13 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "We investigate the theoretical limits of the effect of
                 the quantum interaction distance on the speed of exact
                 quantum addition circuits. For this study, we exploit
                 graph embedding for quantum circuit analysis. We study
                 a logical mapping of qubits and gates of any
                 $\Omega(\log n)$-depth quantum adder circuit for two
                 $n$-qubit registers onto a practical architecture,
                 which limits interaction distance to the nearest
                 neighbors only and supports only one- and two-qubit
                 logical gates. Unfortunately, on the chosen
                 $k$-dimensional practical architecture, we prove that
                 the depth lower bound of any exact quantum addition
                 circuits is no longer $\Omega(\log n)$, but
                 $\Omega(\root k \of n)$.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Goren:2011:DAN,
  author =       "Sezer G{\"o}ren and H. Fatih Ugurdag and Okan Palaz",
  title =        "Defect-Aware Nanocrossbar Logic Mapping through Matrix
                 Canonization Using Two-Dimensional Radix Sort",
  journal =      j-JETC,
  volume =       "7",
  number =       "3",
  pages =        "12:1--12:??",
  month =        aug,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2000502.2000505",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Aug 18 12:25:13 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Nanocrossbars (i.e., nanowire crossbars) offer extreme
                 logic densities but come with very high defect rates;
                 stuck-open/closed, broken nanowires. Achieving
                 reasonable yield and utilization requires logic mapping
                 that is defect-aware even at the crosspoint level. Such
                 logic mapping works with a defect map per each
                 manufactured chip. The problem can be expressed as
                 matching of two bipartite graphs; one for the logic to
                 be implemented and other for the nanocrossbar. This
                 article shows that the problem becomes a Bipartite
                 SubGraph Isomorphism (BSGI) problem within
                 sub-nanocrossbars free of stuck-closed faults. Our
                 heuristic KNS-2DS is an iterative rough canonizer with
                 approximately O(N2) complexity followed by an O(N3)
                 matching algorithm.",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Devadoss:2011:PQT,
  author =       "Rajeswari Devadoss and Kolin Paul and M.
                 Balakrishnan",
  title =        "{p-QCA}: {A} Tiled Programmable Fabric Architecture
                 Using Molecular Quantum-Dot Cellular Automata",
  journal =      j-JETC,
  volume =       "7",
  number =       "3",
  pages =        "13:1--13:??",
  month =        aug,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2000502.2000506",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Aug 18 12:25:13 MDT 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Quantum-dot cellular automata is an interesting
                 computation fabric with many never-seen-before
                 properties. However, no programmable fabric scheme has
                 utilized all these properties effectively. We propose
                 an architecture for a programmable device using
                 molecular QCA which exploits all the specialities of
                 the fabric. The architecture taps the flexibility
                 provided by the clocking system of molecular QCA to
                 build a simple tile-based programmable device with the
                 3-input Majority gate as the fundamental logic
                 element.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Singh:2011:ISI,
  author =       "Montek Singh and Steven M. Nowick",
  title =        "Introduction to Special Issue: Asynchrony in System
                 Design",
  journal =      j-JETC,
  volume =       "7",
  number =       "4",
  pages =        "14:1--14:??",
  month =        dec,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2043643.2043644",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Dec 15 09:46:08 MST 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "14",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Vacca:2011:ASN,
  author =       "Marco Vacca and Mariagrazia Graziano and Maurizio
                 Zamboni",
  title =        "Asynchronous Solutions for Nanomagnetic Logic
                 Circuits",
  journal =      j-JETC,
  volume =       "7",
  number =       "4",
  pages =        "15:1--15:??",
  month =        dec,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2043643.2043645",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Dec 15 09:46:08 MST 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In the years to come new solutions will be required to
                 overcome the limitations of scaled CMOS technology. One
                 approach is to adopt Nano-Magnetic Logic Circuits,
                 highly appealing for their extremely reduced power
                 consumption. Despite the interesting nature of this
                 approach, many problems arise when this technology is
                 considered for real designs. The wire is the most
                 critical of these problems from the circuit
                 implementation point of view. It works as a pipelined
                 interconnection, and its delay in terms of clock cycles
                 depends on its length. Serious complications arise at
                 the design phase, both in terms of synthesis and of
                 physical design.",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Zhang:2011:NPD,
  author =       "Xuefu Zhang and Delong Shang and Fei Xia and Alex
                 Yakovlev",
  title =        "A Novel Power Delivery Method for Asynchronous Loads
                 in Energy Harvesting Systems",
  journal =      j-JETC,
  volume =       "7",
  number =       "4",
  pages =        "16:1--16:??",
  month =        dec,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2043643.2043646",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Dec 15 09:46:08 MST 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "For systems depending on power harvesting, a
                 fundamental contradiction in the power delivery chain
                 has existed between conventional synchronous
                 computational loads requiring relatively stable Vdd and
                 power harvesters unable to supply it. DC/DC conversion
                 has therefore been an integral part of such systems to
                 resolve this contradiction. On the other hand,
                 asynchronous computational loads, in addition to their
                 potential power-saving capabilities, can be made
                 tolerant to a much wider range of Vdd variance. This
                 may open up opportunities for much more energy
                 efficient methods of power delivery. This article
                 presents in-depth investigations into the behavior and
                 performance of different on-chip power delivery methods
                 driving both asynchronous and synchronous loads
                 directly from a harvester source.",
  acknowledgement = ack-nhfb,
  articleno =    "16",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Plana:2011:SDI,
  author =       "Luis A. Plana and David Clark and Simon Davidson and
                 Steve Furber and Jim Garside and Eustace Painkras and
                 Jeffrey Pepper and Steve Temple and John Bainbridge",
  title =        "{SpiNNaker}: Design and Implementation of a {GALS}
                 Multicore {System-on-Chip}",
  journal =      j-JETC,
  volume =       "7",
  number =       "4",
  pages =        "17:1--17:??",
  month =        dec,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2043643.2043647",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Dec 15 09:46:08 MST 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The design and implementation of globally asynchronous
                 locally synchronous systems-on-chip is a challenging
                 activity. The large size and complexity of the systems
                 require the use of computer-aided design (CAD) tools
                 but, unfortunately, most tools do not work adequately
                 with asynchronous circuits. This article describes the
                 successful design and implementation of SpiNNaker, a
                 GALS multicore system-on-chip. The process was
                 completed using commercial CAD tools from synthesis to
                 layout. A hierarchical methodology was devised to deal
                 with the asynchronous sections of the system,
                 encapsulating and validating timing assumptions at each
                 level. The crossbar topology combined with a pipelined
                 asynchronous fabric implementation allows the on-chip
                 network to meet the stringent requirements of the
                 system.",
  acknowledgement = ack-nhfb,
  articleno =    "17",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Galceran-Oms:2011:MTU,
  author =       "Marc Galceran-Oms and Alexander Gotmanov and Jordi
                 Cortadella and Mike Kishinevsky",
  title =        "Microarchitectural Transformations Using Elasticity",
  journal =      j-JETC,
  volume =       "7",
  number =       "4",
  pages =        "18:1--18:??",
  month =        dec,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2043643.2043648",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Dec 15 09:46:08 MST 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Elasticity is a paradigm that tolerates the variations
                 in computation and communication delays. By applying
                 elastic transformations that allow varying the original
                 timing, circuits can be optimized beyond the
                 conventional rigid transformations that do not modify
                 the external timing. Pipelining is one of the classical
                 techniques to improve the throughput of a circuit. This
                 article reveals how elasticity can be effectively and
                 practically used to derive pipelined circuits by using
                 correct-by-construction transformations that can be
                 fully automated. Two designs, one of them industrial,
                 are used to demonstrate how the area-performance
                 trade-off can be explored using elasticity.",
  acknowledgement = ack-nhfb,
  articleno =    "18",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Sheikh:2011:EEP,
  author =       "Basit Riaz Sheikh and Rajit Manohar",
  title =        "{Energy-Efficient} Pipeline Templates for
                 {High-Performance} Asynchronous Circuits",
  journal =      j-JETC,
  volume =       "7",
  number =       "4",
  pages =        "19:1--19:??",
  month =        dec,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2043643.2043649",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Dec 15 09:46:08 MST 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "We present two novel energy-efficient pipeline
                 templates for high throughput asynchronous circuits.
                 The proposed templates, called N-P and N-Inverter
                 pipelines, use a single-track handshake protocol. There
                 are multiple stages of logic within each pipeline. The
                 proposed techniques minimize handshake overheads
                 associated with input tokens and intermediate logic
                 nodes within a pipeline template. Each template can
                 pack a significant amount of logic in a single stage,
                 while still maintaining a fast cycle time of only 18
                 transitions. Noise and timing robustness constraints of
                 our pipelined circuits are quantified across all
                 process corners. We present completion detection scheme
                 based on wide NOR gates, which results in significant
                 latency and energy savings especially as the number of
                 outputs increase.",
  acknowledgement = ack-nhfb,
  articleno =    "19",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Matherat:2011:RCC,
  author =       "Philippe Matherat and Marc-Thierry Jaekel",
  title =        "Relativistic Causality and Clockless Circuits",
  journal =      j-JETC,
  volume =       "7",
  number =       "4",
  pages =        "20:1--20:??",
  month =        dec,
  year =         "2011",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2043643.2043650",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Thu Dec 15 09:46:08 MST 2011",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Time plays a crucial role in the performance of
                 computing systems. The accurate modelling of logical
                 devices, and of their physical implementations,
                 requires an appropriate representation of time and of
                 all properties that depend on this notion. The need for
                 a proper model, particularly acute in the design of
                 clockless delay-insensitive (DI) circuits, leads one to
                 reconsider the classical descriptions of time and of
                 the resulting order and causal relations satisfied by
                 logical operations. This questioning meets the
                 criticisms of classical spacetime formulated by
                 Einstein when founding relativity theory and is
                 answered by relativistic conceptions of time and
                 causality. Applying this approach to clockless circuits
                 and considering the trace formalism, we rewrite
                 Udding's rules, which characterize communications
                 between DI components. We exhibit their intrinsic
                 relation with relativistic causality. For that purpose,
                 we introduce relativistic generalizations of traces,
                 called R-traces, which provide a pertinent description
                 of communications and compositions of DI components.",
  acknowledgement = ack-nhfb,
  articleno =    "20",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Crocker:2012:RPA,
  author =       "Michael Crocker and Michael Niemier and X. Sharon
                 Hu",
  title =        "A Reconfigurable {PLA} Architecture for Nanomagnet
                 Logic",
  journal =      j-JETC,
  volume =       "8",
  number =       "1",
  pages =        "1:1--1:??",
  month =        feb,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2093145.2093146",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Feb 28 16:37:42 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In order to continue the performance and scaling
                 trends that we have come to expect from Moore's Law,
                 many emergent computational models, devices, and
                 technologies are actively being studied to either
                 replace or augment CMOS technology. Nanomagnet Logic
                 (NML) is one such alternative. NML operates at room
                 temperature, it has the potential for low power
                 consumption, and it is CMOS compatible. In this
                 article, we present an NML programmable logic array
                 (PLA) based on a previously proposed reprogrammable
                 quantum-dot cellular automata PLA design. We also
                 discuss the fabrication and simulation validation of
                 the circuit structures unique to the NML PLA, present
                 area, energy, and delay estimates for the NML PLA,
                 compare the area of NML PLAs to other reprogrammable
                 nanotechnologies, and analyze how architectural-level
                 redundancy will affect performance and defect tolerance
                 in NML PLAs.",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Henry:2012:TNH,
  author =       "Michael B. Henry and Leyla Nazhandali",
  title =        "From Transistors to {NEMS}: Highly Efficient
                 Power-Gating of {CMOS} Circuits",
  journal =      j-JETC,
  volume =       "8",
  number =       "1",
  pages =        "2:1--2:??",
  month =        feb,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2093145.2093147",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Feb 28 16:37:42 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "A rapidly growing class of battery constrained
                 electronic applications are those with very long sleep
                 periods, such as structural health monitoring systems,
                 biomedical implants, and wireless border security
                 cameras. The traditional method for sleep-mode power
                 reduction, transistor power gating, has drawbacks,
                 including performance loss and residual leakage. This
                 article presents a thorough evaluation of a new
                 nanotechnology-enabled power gating structure,
                 CMOS-compatible NEMS switches, in the presence of
                 aggressive supply voltage scaling. Due to the infinite
                 off-resistance of the NEMS switches, the average power
                 consumption of an FFT processor performing 1 FFT per
                 hour drops by around 30 times compared to a
                 transistor-based power gating implementation.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Tolbert:2012:MDA,
  author =       "Jeremy R. Tolbert and Pratik Kabali and Simeranjit
                 Brar and Saibal Mukhopadhyay",
  title =        "Modeling and Designing for Accuracy and Energy
                 Efficiency in Wireless Electroencephalography Systems",
  journal =      j-JETC,
  volume =       "8",
  number =       "1",
  pages =        "3:1--3:??",
  month =        feb,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2093145.2093148",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Feb 28 16:37:42 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Remote wireless monitoring of physiological signals
                 has emerged as a key enabler for biotelemetry and can
                 significantly improve the delivery of healthcare.
                 Improving the energy efficiency and battery lifetime of
                 the monitoring units without sacrificing the acquired
                 signal quality is a key challenge in large-scale
                 deployment of bioelectronic systems for remote wireless
                 monitoring. In this article, we present a design
                 methodology for accuracy aware, energy efficient
                 wireless monitoring of electroencephalography (EEG)
                 data. The proposed design performs a real-time accuracy
                 energy trade-off by controlling the volume of
                 transmitted data based on the information content in
                 the EEG signal. We consider the effect of different
                 system parameters in order to design an optimal
                 system.",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Naruse:2012:SDN,
  author =       "Makoto Naruse and Ferdinand Peper and Kouichi Akahane
                 and Naokatsu Yamamoto and Tadashi Kawazoe and Naoya
                 Tate and Motoichi Ohtsu",
  title =        "Skew Dependence of Nanophotonic Devices Based on
                 Optical Near-Field Interactions",
  journal =      j-JETC,
  volume =       "8",
  number =       "1",
  pages =        "4:1--4:??",
  month =        feb,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2093145.2093149",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Feb 28 16:37:42 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "We examine the timing dependence of nanophotonic
                 devices based on optical excitation transfer via
                 optical near-field interactions at the nanometer scale.
                 We theoretically analyze the dynamic behavior of a
                 two-input nanophotonic switch composed of three quantum
                 dots based on a density matrix formalism while assuming
                 arrival-time differences, or skew, between the inputs.
                 The analysis reveals that the nanophotonic switch is
                 resistant to a skew longer than the input signal
                 duration, and the tolerance to skew is asymmetric with
                 respect to the two inputs. The skew dependence is also
                 experimentally examined based on near-field
                 spectroscopy of InGaAs quantum dots, showing good
                 agreement with the theory.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Ye:2012:TBH,
  author =       "Yaoyao Ye and Jiang Xu and Xiaowen Wu and Wei Zhang
                 and Weichen Liu and Mahdi Nikdast",
  title =        "A Torus-Based Hierarchical Optical-Electronic
                 {Network-on-Chip} for Multiprocessor {System-on-Chip}",
  journal =      j-JETC,
  volume =       "8",
  number =       "1",
  pages =        "5:1--5:??",
  month =        feb,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2093145.2093150",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Feb 28 16:37:42 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Networks-on-chip (NoCs) are emerging as a key on-chip
                 communication architecture for multiprocessor
                 systems-on-chip (MPSoCs). Optical communication
                 technologies are introduced to NoCs in order to empower
                 ultra-high bandwidth with low power consumption.
                 However, in existing optical NoCs, communication
                 locality is poorly supported, and the importance of
                 floorplanning is overlooked. These significantly limit
                 the power efficiency and performance of optical NoCs.
                 In this work, we address these issues and propose a
                 torus-based hierarchical hybrid optical-electronic NoC,
                 called THOE. THOE takes advantage of both electrical
                 and optical routers and interconnects in a hierarchical
                 manner. It employs several new techniques including
                 floorplan optimization, an adaptive power control
                 mechanism, low-latency control protocols, and hybrid
                 optical-electrical routers with a low-power optical
                 switching fabric.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Manem:2012:DCM,
  author =       "H. Manem and J. Rajendran and G. S. Rose",
  title =        "Design Considerations for Multilevel {{CMOS\slash}
                 Nano} Memristive Memory",
  journal =      j-JETC,
  volume =       "8",
  number =       "1",
  pages =        "6:1--6:??",
  month =        feb,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2093145.2093151",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Tue Feb 28 16:37:42 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "With technology migration into nano and molecular
                 scales several hybrid CMOS/nano logic and memory
                 architectures have been proposed that aim to achieve
                 high device density with low power consumption. The
                 discovery of the memristor has further enabled the
                 realization of denser nanoscale logic and memory
                 systems by facilitating the implementation of
                 multilevel logic. This work describes the design of
                 such a multilevel nonvolatile memristor memory system,
                 and the design constraints imposed in the realization
                 of such a memory. In particular, the limitations on
                 load, bank size, number of bits achievable per device,
                 placed by the required noise margin for accurately
                 reading and writing the data stored in a device are
                 analyzed.",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Bhunia:2012:ISI,
  author =       "Swarup Bhunia and Darrin J. Young",
  title =        "Introduction to Special Issue on Implantable
                 Electronics",
  journal =      j-JETC,
  volume =       "8",
  number =       "2",
  pages =        "7:1--7:??",
  month =        jun,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2180878.2180879",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Jun 23 12:02:51 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Ko:2012:EHC,
  author =       "Wen H. Ko",
  title =        "Early History and Challenges of Implantable
                 Electronics",
  journal =      j-JETC,
  volume =       "8",
  number =       "2",
  pages =        "8:1--8:??",
  month =        jun,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2180878.2180880",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Jun 23 12:02:51 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Implantable systems for biomedical research and
                 clinical care are now a flourishing field of activities
                 in academia as well as industrial institutions. The
                 broad field includes experimental explorations in
                 electronics, mechanical, chemical, and biological
                 components and systems, and the combination of all
                 these. Today virtually all implants involve both
                 electronic circuits and
                 micro-electro-mechanical-systems (MEMS). This article
                 offers a very brief glance back at the early history of
                 implant electronics in the period from the 1950s to the
                 1970s, by employing selected examples from the author's
                 research. This short review also discusses the
                 challenges of implantable electronics at present, and
                 suggests some potentially important trends in the
                 future research and development of implantable
                 microsystems. It is aimed as an introduction of
                 implantable/attached electronic systems to research
                 engineers that are interested in implantable systems as
                 a section of Biomedical Instrumentations.",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Salam:2012:ICL,
  author =       "Muhammad Tariqus Salam and Mohamad Sawan and Dang Khoa
                 Nguyen",
  title =        "Implantable Closed-Loop Epilepsy Prosthesis: Modeling,
                 Implementation and Validation",
  journal =      j-JETC,
  volume =       "8",
  number =       "2",
  pages =        "9:1--9:??",
  month =        jun,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2180878.2180881",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Jun 23 12:02:51 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this article, we present an implantable closed-loop
                 epilepsy prosthesis, which is dedicated to
                 automatically detect seizure onsets based on
                 intracerebral electroencephalographic (icEEG)
                 recordings from intracranial electrode contacts and
                 provide an electrical stimulation feedback to the same
                 contacts in order to disrupt these seizures. A novel
                 epileptic seizure detector and a dedicated electrical
                 stimulator were assembled together with common
                 recording electrodes to complete the proposed
                 prosthesis. The seizure detector was implemented in
                 CMOS 0.18-$\mu$m by incorporating a new seizure
                 detection algorithm that models time-amplitude and
                 -frequency relationship in icEEG. The detector was
                 validated offline on ten patients with refractory
                 epilepsy and showed excellent performance for early
                 detection of seizures. The electrical stimulator, used
                 for suppressing the developing seizure, is composed of
                 two biphasic channels and was assembled with embedded
                 FPGA in a miniature PCB. The stimulator efficiency was
                 evaluated on cadaveric animal brain tissue in an in
                 vitro morphologic electrical model. Spatial
                 characteristics of the voltage distribution in cortex
                 were assessed in an attempt to identify optimal
                 stimulation parameters required to affect the suspected
                 epileptic focus. The experimental results suggest that
                 lower frequency stimulation parameters cause
                 significant amount of shunting of current through the
                 cerebrospinal fluid; however higher frequency
                 stimulation parameters produce effective spatial
                 voltage distribution with lower stimulation charge.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Sharad:2012:LPA,
  author =       "Mrigank Sharad and Sumeet K. Gupta and Shriram
                 Raghunathan and Pedro P. Irazoqui and Kaushik Roy",
  title =        "Low-Power Architecture for Epileptic Seizure Detection
                 Based on Reduced Complexity {DWT}",
  journal =      j-JETC,
  volume =       "8",
  number =       "2",
  pages =        "10:1--10:??",
  month =        jun,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2180878.2180882",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Jun 23 12:02:51 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this article, we present a low-power,
                 user-programmable architecture for discrete wavelet
                 transform (DWT) based epileptic seizure detection
                 algorithm. A simplified, low-pass filter (LPF)-only-DWT
                 technique is employed in which energy contents of
                 different frequency bands are obtained by subtracting
                 quasi-averaged, consecutive LPF outputs. Training phase
                 is used to identify the range of critical DWT
                 coefficients that are in turn used to set
                 patient-specific system level parameters for minimizing
                 power consumption. The proposed optimizations allow the
                 design to work at significantly lower power in the
                 normal operation mode. The system has been tested on
                 neural data obtained from kainate-treated rats. The
                 design was implemented in TSMC-65nm technology and
                 consumes less than 550-nW power at 250-mV supply.",
  acknowledgement = ack-nhfb,
  articleno =    "10",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Majerus:2012:WUL,
  author =       "Steve J. A. Majerus and Steven L. Garverick and
                 Michael A. Suster and Paul C. Fletter and Margot
                 S. Damaser",
  title =        "Wireless, Ultra-Low-Power Implantable Sensor for
                 Chronic Bladder Pressure Monitoring",
  journal =      j-JETC,
  volume =       "8",
  number =       "2",
  pages =        "11:1--11:??",
  month =        jun,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2180878.2180883",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Jun 23 12:02:51 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The wireless implantable/intracavity micromanometer
                 (WIMM) system was designed to fulfill the unmet need
                 for a chronic bladder pressure sensing device in
                 urological fields such as urodynamics for diagnosis and
                 neuromodulation for bladder control. Neuromodulation in
                 particular would benefit from a wireless bladder
                 pressure sensor which could provide real-time pressure
                 feedback to an implanted stimulator, resulting in
                 greater bladder capacity while using less power. The
                 WIMM uses custom integrated circuitry, a MEMS
                 transducer, and a wireless antenna to transmit pressure
                 telemetry at a rate of 10 Hz. Aggressive power
                 management techniques yield an average current draw of
                 $9 \mu$A from a 3.6-Volt micro-battery, which minimizes
                 the implant size. Automatic pressure offset
                 cancellation circuits maximize the sensing dynamic
                 range to account for drifting pressure offset due to
                 environmental factors, and a custom telemetry protocol
                 allows transmission with minimum overhead. Wireless
                 operation of the WIMM has demonstrated that the
                 external receiver can receive the telemetry packets,
                 and the low power consumption allows for at least 24
                 hours of operation with a 4-hour wireless recharge
                 session.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Huang:2012:IRD,
  author =       "Yu-Jie Huang and Hsin-Hung Liao and Pen-Li Huang and
                 Tao Wang and Yao-Joe Yang and Yao-Hong Wang and
                 Shey-Shi Lu",
  title =        "An Implantable Release-on-Demand {CMOS} Drug Delivery
                 {SoC} Using Electrothermal Activation Technique",
  journal =      j-JETC,
  volume =       "8",
  number =       "2",
  pages =        "12:1--12:??",
  month =        jun,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2180878.2180884",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Jun 23 12:02:51 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "An implantable system-on-a-chip (SoC) integrating
                 controller/actuation circuitry and 8 individually
                 addressable drug reservoirs is proposed for on-demand
                 drug delivery. It is implemented by standard 0.35- \mu
                 m CMOS technology and post-IC processing. The post-IC
                 processing includes deposition of metallic membranes
                 (200{\AA} Pt/3000{\AA} Ti/200{\AA} Pt) to cap the drug
                 reservoirs, deep dry etching to carve drug reservoirs
                 in silicon as drug containers, and PDMS layer bonding
                 to enlarge the drug storage. Based on electrothermal
                 activation technique, drug releases can be precisely
                 controlled by wireless signals. The wireless
                 controller/actuation circuits including on-off keying
                 (OOK) receiver, microcontroller unit, clock generator,
                 power-on-reset circuit, and switch array are integrated
                 on the same chip, providing patients the ability of
                 remote drug activation and noninvasive therapy
                 modification. Implanted by minimally invasive surgery,
                 this SoC can be used for the precise drug dosing of
                 localized treatment, such as the cancer therapy, or the
                 immediate medication to some emergent diseases, such as
                 heart attack. In vitro experimental results show that
                 the reservoir content can be released successfully
                 through the rupture of the membrane which is appointed
                 by received wireless commands.",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Sun:2012:NMD,
  author =       "Zhenyu Sun and Xiang Chen and Yaojun Zhang and Hai Li
                 and Yiran Chen",
  title =        "Nonvolatile Memories as the Data Storage System for
                 Implantable {ECG} Recorder",
  journal =      j-JETC,
  volume =       "8",
  number =       "2",
  pages =        "13:1--13:??",
  month =        jun,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2180878.2180885",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Sat Jun 23 12:02:51 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this article, we propose a data storage system with
                 the emerging nonvolatile memory technologies used for
                 the implantable electrocardiography (ECG) recorder. The
                 proposed storage system can record the digitalized
                 real-time ECG waveforms continuously inside the
                 implantable device and export the stored data to
                 external reader periodically to obtain a long-term
                 backup. Spin transfer torque random access memory
                 (STT-RAM) and spintronic memristor are selected as the
                 storage elements for their nonvolatility, high density,
                 high reliability, low power consumption, good
                 scalability, and CMOS technology compatibility. The new
                 read and write schemes of STT-RAM and spintronic
                 memristors are presented and optimized to fit the
                 specific application scenario. The tradeoffs among data
                 accuracy, chip area, and read/write energy for the
                 different technologies are thoroughly analyzed and
                 compared. Our simulation results show the configuration
                 with a data sampling rate (e.g., 128 Hz) and a
                 quantization resolution (e.g., 12 bits) can record
                 18-hour real-time data within ~ 3.6-mm$^2$ chip area
                 when the data storage is built with single-level cell
                 (SLC) STT-RAMs. Daily energy consumption is 5.46 mJ.
                 Utilizing the multilevel cell (MLC) STT-RAMs or the
                 spintronic memristors as the storage elements can
                 further reduce the chip area and decrease energy
                 dissipation.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Mohanty:2012:SSN,
  author =       "Saraju P. Mohanty",
  title =        "Special section on new circuit and architecture-level
                 solutions for multidiscipline systems",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "14:1--14:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287697",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "14",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Srivastava:2012:CLV,
  author =       "Ashok Srivastava and Yao Xu and Yang Liu and Ashwani
                 K. Sharma and Clay Mayberry",
  title =        "{CMOS LC} voltage controlled oscillator design using
                 multiwalled and single-walled carbon nanotube wire
                 inductors",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "15:1--15:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287698",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "We have utilized our Multiwalled Carbon NanoTube
                 (MWCNT) and Single-Walled Carbon NanoTube (SWCNT)
                 bundle interconnects model in a widely used $\pi$ model
                 to study the performances of MWCNT and SWCNT bundle
                 wire inductors and compared these with copper (Cu)
                 inductors. The calculation results show that the
                 Q-factors of Carbon NanoTube (CNT) wire (SWCNT bundle
                 and MWCNT) inductors are higher than that of the Cu
                 wire inductor. This is mainly due to much lower
                 resistance of CNT and negligible skin effect in carbon
                 nanotubes at higher frequencies. The application of CNT
                 wire inductor in LC VCO is also studied and the
                 Cadence/Spectre simulations show that VCOs with CNT
                 bundle wire inductors have significantly improved
                 performance such as the higher oscillation frequency
                 and lower phase noise due to their smaller resistances
                 and higher Q-factors. It is also noticed that CMOS LC
                 VCO using a SWCNT bundle wire inductor has better
                 performance when compared with the performance of LC
                 VCO using the MWCNT wire inductor due to its lower
                 resistance and higher Q-factor.",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Mahalingam:2012:DCS,
  author =       "Venkataraman Mahalingam and Nagarajan Ranganathan and
                 Ransford {Hyman, Jr.}",
  title =        "Dynamic clock stretching for variation compensation in
                 {VLSI} circuit design",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "16:1--16:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287699",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In the nanometer era, process, voltage, and
                 temperature variations are dominating circuit
                 performance, power, and yield. Over the past few years,
                 statistical optimization methods have been effective in
                 improving yield in the presence of uncertainty due to
                 process variations. However, statistical methods
                 overconsume resources, even in the absence of
                 variations. Hence, to facilitate a better
                 performance-power-yield trade-off, techniques that can
                 dynamically enable variation compensation are becoming
                 necessary. In this article, we propose a dynamic
                 technique that controls the instance of data capture in
                 critical path memory flops, by delaying the clock edge
                 trigger. The methodology employs a dynamic delay
                 detection circuit to identify the uncertainty in delay
                 due to variations and stretches the clock in the
                 destination flip-flops. The delay detection circuit
                 uses a latch and set of combinational gates to
                 dynamically detect and create the slack needed to
                 accommodate the delay due to variations. The Clock
                 Stretching Logic (CSL) is added only to paths, which
                 have a high probability of failure in the presence of
                 variations. The proposed methodology improves the
                 timing yield of the circuit without significant
                 overcompensation. The methodology approach was
                 simulated using Synopsys design tools for circuit
                 synthesis and Cadence tools for placement and routing
                 of the design. Extraction of parasitic of timing
                 information was parsed using Perl scripts and simulated
                 using a simulation program generated in C++.
                 Experimental results based on Monte-Carlo simulations
                 on benchmark circuits indicate considerable improvement
                 in timing yield with negligible area overhead.",
  acknowledgement = ack-nhfb,
  articleno =    "16",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Roy:2012:CAL,
  author =       "Sudip Roy and Debasis Mitra and Bhargab B.
                 Bhattacharya and Krishnendu Chakrabarty",
  title =        "Congestion-aware layout design for high-throughput
                 digital microfluidic biochips",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "17:1--17:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287700",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Potential applications of digital microfluidic (DMF)
                 biochips now include several areas of real-life
                 applications like environmental monitoring, water and
                 air pollutant detection, and food processing to name a
                 few. In order to achieve sufficiently high throughput
                 for these applications, several instances of the same
                 bioassay may be required to be executed concurrently on
                 different samples. As a straightforward implementation,
                 several identical biochips can be integrated on a
                 single substrate as a multichip to execute the assay
                 for various samples concurrently. Controlling
                 individual electrodes of such a chip by independent
                 pins may not be acceptable since it increases the cost
                 of fabrication. Thus, in order to keep the overall
                 pin-count within an acceptable bound, all the
                 respective electrodes of these individual pieces are
                 connected internally underneath the chip so that they
                 can be controlled with a single external control pin.
                 In this article, we present an orientation strategy for
                 layout of a multichip that reduces routing congestion
                 and consequently facilitates wire routing for the
                 electrode array. The electrode structure of the
                 individual pieces of the multichip may be either
                 direct-addressable or pin-constrained. The method also
                 supports a hierarchical approach to wire routing that
                 ensures scalability. In this scheme, the size of the
                 biochip in terms of the total number of electrodes may
                 be increased by a factor of four by increasing the
                 number of routing layers by only one. In general, for a
                 multichip with 4 $^n$ identical blocks, ( n + 1) layers
                 are sufficient for wire routing.",
  acknowledgement = ack-nhfb,
  articleno =    "17",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Komerath:2012:RBP,
  author =       "Narayanan Komerath and Aravinda Kar",
  title =        "Retail beamed power using millimeter waves: Survey",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "18:1--18:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287701",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Retail delivery of electric power through millimeter
                 waves is relevant in developing areas where the market
                 for communication devices outpaces the power grid
                 infrastructure. It is also a critical component of an
                 evolutionary path towards terrestrial and space-based
                 renewable power generation. Narrow-band power can be
                 delivered as focused beams to receivers near end-users,
                 from central power plants, rural distribution points,
                 UAVs, tethered aerostats, stratospheric airship
                 platforms, or space satellites. The article surveys the
                 available knowledge base on millimeter wave beamed
                 power delivery. It then considers design requirements
                 for a retail beamed power architecture, in the context
                 of rural India where power delivery is lagging behind
                 the demand growth for connectivity. A survey of
                 technology developments relevant to millimeter wave
                 beaming is conducted, and indicates that massive,
                 mass-produced solid-state arrays capable of achieving
                 good efficiency and cost effectiveness are possible in
                 the near term to enable such retail power beaming
                 architectures.",
  acknowledgement = ack-nhfb,
  articleno =    "18",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Palaniswamy:2012:EHI,
  author =       "Ashok Kumar Palaniswamy and Spyros Tragoudas",
  title =        "An efficient heuristic to identify threshold logic
                 functions",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "19:1--19:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287702",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "A fast method to identify the given Boolean function
                 as a threshold function with weight assignment is
                 introduced. It characterizes the function based on the
                 parameters that have been defined in the literature.
                 The proposed method is capable to quickly characterize
                 all functions that have less than eight inputs and has
                 been shown to operate fast for functions with as many
                 as forty inputs. Furthermore, comparisons with other
                 existing heuristic methods show huge increase in the
                 number of threshold functions identified, and drastic
                 reduction in time and complexity.",
  acknowledgement = ack-nhfb,
  articleno =    "19",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Xu:2012:EPV,
  author =       "Hu Xu and Vasilis F. Pavlidis and Giovanni {De
                 Micheli}",
  title =        "Effect of process variations in {$3$D} global clock
                 distribution networks",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "20:1--20:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287703",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In three-dimensional (3D) integrated circuits, the
                 effect of process variations on clock skew differs from
                 2D circuits. The combined effect of inter-die and
                 intra-die process variations on the design of 3D clock
                 distribution networks is considered in this article. A
                 statistical clock skew model incorporating both the
                 systematic and random components of process variations
                 is employed to describe this effect. Two regular 3D
                 clock tree topologies are investigated and compared in
                 terms of clock skew variation. The statistical skew
                 model used to describe clock skew variations is
                 verified through Monte-Carlo simulations. The clock
                 skew is shown to change in different ways with the
                 number of planes forming the 3D IC and the clock
                 network architecture. Simulations based on a 45-nm CMOS
                 technology show that the maximum standard deviation of
                 clock skew can vary from 15 ps to 77 ps. Results
                 indicate that simply increasing the number of planes of
                 a 3D IC does not necessarily lead to lower skew
                 variation and higher operating frequencies. A
                 multigroup 3D clock tree topology is proposed to
                 effectively mitigate the variability of clock skew.
                 Tradeoffs between the investigated 3D clock
                 distribution networks and the number of planes
                 comprising a 3D circuit are discussed and related
                 design guidelines are offered. The skew variation in 3D
                 clock trees is also compared with the skew variation of
                 clock grids.",
  acknowledgement = ack-nhfb,
  articleno =    "20",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Kursun:2012:STT,
  author =       "Eren Kursun and Jamil Wakil and Mukta Farooq and
                 Robert Hannon",
  title =        "Spatial and temporal thermal characterization of
                 stacked multicore architectures",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "21:1--21:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287704",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Three-dimensional integration provides a new way of
                 performance growth for microprocessor architectures.
                 While a recent studies report promising performance
                 improvement numbers, majority of the processor stacking
                 options are thermally-limited. Elevated stack
                 temperatures have significant effect on the overall
                 energy efficiency and reliability of the processor;
                 they also limit the potential peak performance
                 improvement from the 3D implementation. Thermal
                 characteristics of 3D stacks differ from 2D processors
                 in various ways including: the nature of heat
                 dissipation throughout the stack, thermal conductivity
                 of the 3D structures such as micro-C4 layers, and
                 hotspot interactions among layers. The intensity of the
                 corresponding thermal problems is highly dependent on
                 the 3D technology, processor and stack parameters. In
                 this study we focus on spatial and temporal thermal
                 characteristics of 3D multicore architectures using
                 high-fidelity technology and processor models. Our
                 experimental results highlight the need for integrating
                 detailed thermal models in the design flow, starting
                 with the early design stages. In addition, the reduced
                 time constants and elevated on-chip temperatures
                 indicate faster response time requirements for dynamic
                 thermal management in processor stacking options.",
  acknowledgement = ack-nhfb,
  articleno =    "21",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Liu:2012:RAP,
  author =       "Bao Liu and Xuemei Chen and Fiona Teshome",
  title =        "Resilient and adaptive performance logic",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "22:1--22:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287705",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "As VLSI technology continues scaling, increasingly
                 significant parametric variations and increasingly
                 prevalent defects present unprecedented challenges to
                 VLSI design at nanometer scale. Specifically,
                 performance variability has hindered performance
                 scaling, while soft errors become an emerging problem
                 for logic computation at recent technology nodes. In
                 this article, we leverage the existing Totally
                 Self-Checking (TSC)/Strongly Fault-Secure (SFS) logic
                 design techniques, and propose Resilient and Adaptive
                 Performance (RAP) logic for maximum adaptive
                 performance and soft error resilience in nanoscale
                 computing. RAP logic clears all timing errors in the
                 absence of external soft errors, albeit at a higher
                 area/power cost compared with Razor logic. Our
                 experimental results further show that dual-rail static
                 (Domino) RAP logic outperforms alternative
                 Delay-Insensitive (DI) code-based static (Domino) RAP
                 logic with less area, higher performance, and lower
                 power consumption for the large test cases, and
                 achieves an average of 2.29(2.41)$\times$ performance
                 boost, 2.12(1.91)$\times$ layout area, and
                 2.38(2.34)$\times$ power consumption compared with the
                 traditional minimum area static logic based on the
                 Nangate 45-nm open cell library.",
  acknowledgement = ack-nhfb,
  articleno =    "22",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chang:2012:PED,
  author =       "Kevin Chang and Sujay Deb and Amlan Ganguly and Xinmin
                 Yu and Suman Prasad Sah and Partha Pratim Pande and
                 Benjamin Belzer and Deukhyoun Heo",
  title =        "Performance evaluation and design trade-offs for
                 wireless network-on-chip architectures",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "23:1--23:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287706",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Massive levels of integration are making modern
                 multicore chips all pervasive in several domains. High
                 performance, robustness, and energy-efficiency are
                 crucial for the widespread adoption of such platforms.
                 Networks-on-Chip (NoCs) have emerged as communication
                 backbones to enable a high degree of integration in
                 multicore Systems-on-Chip (SoCs). Despite their
                 advantages, an important performance limitation in
                 traditional NoCs arises from planar metal
                 interconnect-based multihop links with high latency and
                 power consumption. This limitation can be addressed by
                 drawing inspiration from the evolution of natural
                 complex networks, which offer great performance-cost
                 trade-offs. Analogous with many natural complex
                 systems, future multicore chips are expected to be
                 hierarchical and heterogeneous in nature as well. In
                 this article we undertake a detailed performance
                 evaluation for hierarchical small-world NoC
                 architectures where the long-range communications links
                 are established through the millimeter-wave wireless
                 communication channels. Through architecture-space
                 exploration in conjunction with novel power-efficient
                 on-chip wireless link design, we demonstrate that it is
                 possible to improve performance of conventional NoC
                 architectures significantly without incurring high area
                 overhead.",
  acknowledgement = ack-nhfb,
  articleno =    "23",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Choi:2012:DQA,
  author =       "Byung-Soo Choi and Rodney {Van Meter}",
  title =        "A {$\Theta (\sqrt n)$}-depth quantum adder on the
                 {$2$D NTC} quantum computer architecture",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "24:1--24:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287707",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this work, we propose an adder for the
                 2-Dimensional Nearest-Neighbor, Two-Qubit gate,
                 Concurrent (2D NTC) architecture, designed to match the
                 architectural constraints of many quantum computing
                 technologies. The chosen architecture allows the layout
                 of logical qubits in two dimensions with {\&}sqrt; n
                 columns where each column has {\&}sqrt; n qubits and
                 the concurrent execution of one- and two-qubit gates
                 with nearest-neighbor interaction only. The proposed
                 adder works in three phases. In the first phase, the
                 first column generates the summation output and the
                 other columns do the carry-lookahead operations. In the
                 second phase, these intermediate values are propagated
                 from column to column, preparing for computation of the
                 final carry for each register position. In the last
                 phase, each column, except the first one, generates the
                 summation output using this column-level carry. The
                 depth and the number of qubits of the proposed adder
                 are $\Theta(\sqrt n)$ and $O(n)$, respectively. The
                 proposed adder executes faster than the adders designed
                 for the 1D NTC architecture when the length of the
                 input registers $n$ is larger than 51.",
  acknowledgement = ack-nhfb,
  articleno =    "24",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Huang:2012:PDT,
  author =       "Jiale Huang and Minhao Zhu and Shengqi Yang and Pallav
                 Gupta and Wei Zhang and Steven M. Rubin and Gilda
                 Garret{\'o}n and Jin He",
  title =        "A physical design tool for carbon nanotube
                 field-effect transistor circuits",
  journal =      j-JETC,
  volume =       "8",
  number =       "3",
  pages =        "25:1--25:??",
  month =        aug,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2287696.2287708",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Mon Aug 20 15:17:55 MDT 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this article, we present a graphical Computer-Aided
                 Design (CAD) environment for the design, analysis, and
                 layout of Carbon NanoTube (CNT) Field-Effect Transistor
                 (CNFET) circuits. This work is motivated by the fact
                 that such a tool currently does not exist in the public
                 domain for researchers. Our tool has been integrated
                 within Electric a very powerful, yet free CAD system
                 for custom design of Integrated Circuits (ICs). The
                 tool supports CNFET schematic and layout entry, rule
                 checking, and HSpice/VerilogA netlist generation. We
                 provide users with a customizable CNFET technology
                 library with the ability to specify $\lambda$ -based
                 design rules. We showcase the capabilities of our tool
                 by demonstrating the design of a large CNFET standard
                 cell and components library. Meanwhile, HSPICE
                 simulations also have been presented for cell library
                 characterization. We hope that the availability of this
                 tool will invigorate the CAD community to explore novel
                 ideas in CNFET circuit design.",
  acknowledgement = ack-nhfb,
  articleno =    "25",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Pande:2012:ISI,
  author =       "Partha Pratim Pande and Amlan Ganguly",
  title =        "Introduction to the special issue on sustainable and
                 green computing systems",
  journal =      j-JETC,
  volume =       "8",
  number =       "4",
  pages =        "26:1--26:??",
  month =        oct,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2367736.2367737",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Nov 28 17:25:59 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "26",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Banerjee:2012:TNZ,
  author =       "Prithviraj Banerjee and Chandrakant Patel and Cullen
                 Bash and Amip Shah and Martin Arlitt",
  title =        "Towards a net-zero data center",
  journal =      j-JETC,
  volume =       "8",
  number =       "4",
  pages =        "27:1--27:??",
  month =        oct,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2367736.2367738",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Nov 28 17:25:59 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "A world consisting of billions of service-oriented
                 client devices and thousands of data centers can
                 deliver a diverse range of services, from social
                 networking to management of our natural resources.
                 However, these services must scale in order to meet the
                 fundamental needs of society. To enable such scaling,
                 the total cost of ownership of the data centers that
                 host the services and comprise the vast majority of
                 service delivery costs will need to be reduced. As
                 energy drives the total cost of ownership of data
                 centers, there is a need for a new paradigm in design
                 and management of data centers that minimizes energy
                 used across their lifetimes, from ``cradle to cradle''.
                 This tutorial article presents a blueprint for a
                 ``net-zero data center'': one that offsets any
                 electricity used from the grid via adequate on-site
                 power generation that gets fed back to the grid at a
                 later time. We discuss how such a data center addresses
                 the total cost of ownership, illustrating that contrary
                 to the oft-held view of sustainability as ``paying more
                 to be green'', sustainable data centers-built on a
                 framework that focuses on integrating supply and demand
                 management from end-to-end-can concurrently lead to
                 lowest cost and lowest environmental impact.",
  acknowledgement = ack-nhfb,
  articleno =    "27",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Garg:2012:TDL,
  author =       "Siddharth Garg and Diana Marculescu and Radu
                 Marculescu",
  title =        "Technology-driven limits on runtime power management
                 algorithms for multiprocessor systems-on-chip",
  journal =      j-JETC,
  volume =       "8",
  number =       "4",
  pages =        "28:1--28:??",
  month =        oct,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2367736.2367739",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Nov 28 17:25:59 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Runtime power management is a critical technique for
                 reducing the energy footprint of digital electronic
                 devices and enabling sustainable computing, since it
                 allows electronic devices to dynamically adapt their
                 power and energy consumption to meet performance
                 requirements. In this article, we consider the case of
                 MultiProcessor Systems-on-Chip (MPSoC) implemented
                 using multiple Voltage and Frequency Islands (VFIs)
                 relying on fine-grained Dynamic Voltage and Frequency
                 Scaling (DVFS) to reduce the system power dissipation.
                 In particular, we present a framework to theoretically
                 analyze the impact of three important technology-driven
                 constraints; (i) reliability-driven upper limits on the
                 maximum supply voltage; (ii) inductive noise-driven
                 constraints on the maximum rate of change of
                 voltage/frequency; and (iii) the impact of
                 manufacturing process variations on the performance of
                 DVFS control for multiple VFI MPSoCs. The proposed
                 analysis is general, in the sense that it is not bound
                 to a specific DVFS control algorithm, but instead
                 focuses on theoretically bounding the performance that
                 any DVFS controller can possibly achieve. Our
                 experimental results on real and synthetic benchmarks
                 show that in the presence of reliability- and
                 temperature-driven constraints on the maximum frequency
                 and maximum frequency increment, any DVFS control
                 algorithm will lose up to 87\% performance in terms of
                 the number of steps required to reach a reference
                 steady state. In addition, increasing process
                 variations can lead to up to 60\% of fabricated chips
                 being unable to meet the specified DVFS control
                 specifications, irrespective of the DVFS algorithm
                 used. Nonetheless, we note that although conventional
                 DVFS might become less effective with technology
                 scaling, it will continue to play an important role in
                 the context of emerging power management techniques,
                 for example, for massively parallel multiprocessor
                 systems where only a subset of cores can be turned on
                 at any given point of time due to total power
                 constraints.",
  acknowledgement = ack-nhfb,
  articleno =    "28",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Ghidini:2012:EEM,
  author =       "Giacomo Ghidini and Sajal K. Das",
  title =        "Energy-efficient {Markov} chain-based duty cycling
                 schemes for greener wireless sensor networks",
  journal =      j-JETC,
  volume =       "8",
  number =       "4",
  pages =        "29:1--29:??",
  month =        oct,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2367736.2367740",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Nov 28 17:25:59 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "To extend the lifetime of a wireless sensor network,
                 sensor nodes usually duty cycle between dormant and
                 active states. Duty cycling schemes are often evaluated
                 in terms of connection delay, connection duration, and
                 duty cycle. In this article, we show with experiments
                 on Sun SPOT sensors that duty cycling time (energy)
                 efficiency, that is, the ratio of time (energy)
                 employed in ancillary operations when switching from
                 and into deep sleep mode, is an important performance
                 metric too. We propose a novel randomized duty cycling
                 scheme based on Markov chains with the goal of (i)
                 reducing the connection delay, while maintaining a
                 given time (energy) efficiency, or (ii) keeping a
                 constant connection delay, while increasing the time
                 (energy) efficiency. Analytical and experimental
                 results demonstrate that the Markov chain-based scheme
                 can improve the performance in terms of connection
                 delay without affecting the time efficiency, or vice
                 versa, as opposed to the trade-off observed in
                 traditional schemes. We extend the proposed duty
                 cycling scheme to a partially randomized scheme, where
                 wireless nodes can switch into active state beyond
                 their schedules when their neighbors are active to
                 anticipate message forwarding. The analytical and
                 experimental results confirm the relationship between
                 connection delay and time efficiency also for this
                 scheme.",
  acknowledgement = ack-nhfb,
  articleno =    "29",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Sego:2012:IDC,
  author =       "Landon H. Sego and Andr{\'e}s M{\'a}rquez and Andrew
                 Rawson and Tahir Cader and Kevin Fox and William
                 I. {Gustafson, Jr.} and Christopher J. Mundy",
  title =        "Implementing the data center energy productivity
                 metric",
  journal =      j-JETC,
  volume =       "8",
  number =       "4",
  pages =        "30:1--30:??",
  month =        oct,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2367736.2367741",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Nov 28 17:25:59 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "As data centers proliferate in size and number, the
                 endeavor to improve their energy efficiency and
                 productivity is becoming increasingly important. We
                 discuss the properties of a number of the proposed
                 metrics of energy efficiency and productivity. In
                 particular, we focus on the Data Center Energy
                 Productivity (DCeP) metric, which is the ratio of
                 useful work produced by the data center to the energy
                 consumed performing that work. We describe our approach
                 for using DCeP as the principal outcome of a designed
                 experiment using a highly instrumented,
                 high-performance computing data center. We found that
                 DCeP was successful in clearly distinguishing different
                 operational states in the data center, thereby
                 validating its utility as a metric for identifying
                 configurations of hardware and software that would
                 improve (or even maximize) energy productivity. We also
                 discuss some of the challenges and benefits associated
                 with implementing the DCeP metric, and we examine the
                 efficacy of the metric in making comparisons within a
                 data center and among data centers.",
  acknowledgement = ack-nhfb,
  articleno =    "30",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Anagnostopoulou:2012:BAM,
  author =       "Vlasia Anagnostopoulou and Susmit Biswas and Heba
                 Saadeldeen and Alan Savage and Ricardo Bianchini and
                 Tao Yang and Diana Franklin and Frederic T. Chong",
  title =        "Barely alive memory servers: Keeping data active in a
                 low-power state",
  journal =      j-JETC,
  volume =       "8",
  number =       "4",
  pages =        "31:1--31:??",
  month =        oct,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2367736.2367742",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Nov 28 17:25:59 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Current resource provisioning schemes in Internet
                 services leave servers less than 50\% utilized almost
                 all the time. At this level of utilization, the
                 servers' energy efficiency is substantially lower than
                 at peak utilization. A solution to this problem could
                 be dynamically consolidating workloads into fewer
                 servers and turning others off. However, services
                 typically resist doing so, because of high response
                 times during reactivation in handling traffic spikes.
                 Moreover, services often want the memory and/or storage
                 of all servers to be readily available at all times. In
                 this article, we propose a family of barely alive
                 active low-power server states that facilitates both
                 fast reactivation and access to memory while in a
                 low-power state. We compare these states to previously
                 proposed active and idle states. In particular, we
                 investigate the impact of load bursts in each
                 energy-saving scheme. We also evaluate the additional
                 benefits of memory access under low-power states with a
                 study of a search service using a cooperative
                 main-memory cache. Finally, we propose a system that
                 combines a barely-alive state with the off state. We
                 find that the barely alive states can reduce service
                 energy consumption by up to 38\%, compared to an
                 energy-oblivious system. We also find that these energy
                 savings are consistent across a large parameter
                 space.",
  acknowledgement = ack-nhfb,
  articleno =    "31",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Sheikh:2012:EPA,
  author =       "Hafiz Fahad Sheikh and Hengxing Tan and Ishfaq Ahmad
                 and Sanjay Ranka and Phanisekhar Bv",
  title =        "Energy- and performance-aware scheduling of tasks on
                 parallel and distributed systems",
  journal =      j-JETC,
  volume =       "8",
  number =       "4",
  pages =        "32:1--32:??",
  month =        oct,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2367736.2367743",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Nov 28 17:25:59 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Enabled by high-speed networking in commercial,
                 scientific, and government settings, the realm of high
                 performance is burgeoning with greater amounts of
                 computational and storage resources. Large-scale
                 systems such as computational grids consume a
                 significant amount of energy due to their massive
                 sizes. The energy and cooling costs of such systems are
                 often comparable to the procurement costs over a year
                 period. In this survey, we will discuss allocation and
                 scheduling algorithms, systems, and software for
                 reducing power and energy dissipation of workflows on
                 the target platforms of single processors, multicore
                 processors, and distributed systems. Furthermore,
                 recent research achievements will be investigated that
                 deal with power and energy efficiency via different
                 power management techniques and application scheduling
                 algorithms. The article provides a comprehensive
                 presentation of the architectural, software, and
                 algorithmic issues for energy-aware scheduling of
                 workflows on single, multicore, and parallel
                 architectures. It also includes a systematic taxonomy
                 of the algorithms developed in the literature based on
                 the overall optimization goals and characteristics of
                 applications.",
  acknowledgement = ack-nhfb,
  articleno =    "32",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Kant:2012:EDC,
  author =       "Krishna Kant and Muthukumar Murugan and David H. C.
                 Du",
  title =        "Enhancing data center sustainability through
                 energy-adaptive computing",
  journal =      j-JETC,
  volume =       "8",
  number =       "4",
  pages =        "33:1--33:??",
  month =        oct,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2367736.2367744",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Nov 28 17:25:59 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The sustainability concerns of Information Technology
                 (IT) go well beyond energy-efficient computing and
                 require techniques for minimizing environmental impact
                 of IT infrastructure over its entire life-cycle.
                 Traditionally, IT infrastructure is overdesigned at all
                 levels from chips to entire data centers and ecosystem;
                 the paradigm explored in this article is to replace
                 overdesign with rightsizing coupled with smarter
                 control, henceforth referred to as Energy-Adaptive
                 Computing or EAC. The article lays out the challenges
                 of EAC in various environments in terms of the
                 adaptation of the workload and the infrastructure to
                 cope with energy and cooling deficiencies. The article
                 then focuses on implementing EAC in a data center
                 environment, and addresses the problem of simultaneous
                 energy demand and energy supply regulation at multiple
                 levels, work, from servers to the entire data center.
                 The proposed control scheme adapts the assignments of
                 tasks to servers in a way that can cope with the
                 varying energy limitations. The article also presents
                 some experimental results to show how the scheme can
                 continue to meet Quality of Service (QoS) requirements
                 of tasks under energy limitations.",
  acknowledgement = ack-nhfb,
  articleno =    "33",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Abbasi:2012:DGD,
  author =       "Zahra Abbasi and Tridib Mukherjee and Georgios
                 Varsamopoulos and Sandeep K. S. Gupta",
  title =        "{DAHM}: a green and dynamic {Web} application hosting
                 manager across geographically distributed data
                 centers",
  journal =      j-JETC,
  volume =       "8",
  number =       "4",
  pages =        "34:1--34:??",
  month =        oct,
  year =         "2012",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2367736.2367745",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Nov 28 17:25:59 MST 2012",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Dynamic Application Hosting Management (DAHM) is
                 proposed for geographically distributed data centers,
                 which decides on the number of active servers and on
                 the workload share of each data center. DAHM achieves
                 cost-efficient application hosting by taking into
                 account: (i) the spatio-temporal variation of energy
                 cost, (ii) the data center computing and cooling energy
                 efficiency, (iii) the live migration cost, and (iv) any
                 SLA violations due to migration overhead or network
                 delay. DAHM is modeled as fixed-charge min-cost flow
                 and mixed integer programming for stateless and
                 stateful applications, respectively, and it is shown
                 NP-hard. We also develop heuristic algorithms and
                 prove, when applications are stateless and servers have
                 an identical power consumption model, that the
                 approximation ratio on the minimum total cost is
                 bounded by the number of data centers. Further, the
                 heuristics are evaluated in a simulation study using
                 realistic parameter data; compared to a
                 performance-oriented application assignment, that is,
                 hosting at the data center with the least delay, the
                 potential cost savings of DAHM reaches 33\%. The
                 savings come from reducing the total number of active
                 servers as well as leveraging the cost efficiency of
                 data centers. Through the simulation study, the article
                 further explores how relaxing the delay requirement for
                 a small fraction of users can increase the cost savings
                 of DAHM.",
  acknowledgement = ack-nhfb,
  articleno =    "34",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Srinivasan:2013:NAF,
  author =       "S. Srinivasan and V. Kamakoti and A. Bhattacharya",
  title =        "A Novel Algorithm for Fast Synthesis of {DNA} Probes
                 on Microarrays",
  journal =      j-JETC,
  volume =       "9",
  number =       "1",
  pages =        "1:1--1:??",
  month =        feb,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2422094.2422095",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Feb 20 16:42:57 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "DNA microarrays are used extensively for biochemical
                 analysis that includes genomics and drug discovery.
                 This increased usage demands large microarrays, thus
                 complicating their computer aided design (CAD) and
                 manufacturing methodologies. One such time-consuming
                 design problem is to minimize the border length of
                 masks used during the manufacture of microarrays. From
                 the manufacturing point of view the border length of
                 masks is one of the crucial parameters determining the
                 reliability of the microarray. This article presents a
                 novel algorithm for synthesis (placement and embedding)
                 of microarrays, which consumes significantly less time
                 than the best algorithm reported in the literature,
                 while maintaining the quality (border length of masks)
                 of the result. The proposed technique uses only a part
                 of each probe to decide on the placement and the
                 remaining parts for deciding on the embedding sequence.
                 This is in contrast to the earlier methods that
                 considered the entire probe for both placement and
                 embedding. The second novelty of the proposed technique
                 is the preclassification (prior to placement and
                 embedding) of probes based on their prefixes. This
                 decreases the complexity of the problem of deciding the
                 next probe to be placed from that involving computation
                 of Hamming distance between all probes (as used in
                 earlier approaches) to the one involving searching of
                 nonempty cells on a constant size grid array. The
                 proposed algorithm is $43 \times $ faster than the best
                 reported in the literature for the case of synthesizing
                 a microarray with 250,000 probes and further exhibits
                 linear behavior in terms of computation time for larger
                 microarrays.",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Maftei:2013:MBS,
  author =       "Elena Maftei and Paul Pop and Jan Madsen",
  title =        "Module-Based Synthesis of Digital Microfluidic
                 Biochips with Droplet-Aware Operation Execution",
  journal =      j-JETC,
  volume =       "9",
  number =       "1",
  pages =        "2:1--2:??",
  month =        feb,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2422094.2422096",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Feb 20 16:42:57 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Microfluidic biochips represent an alternative to
                 conventional biochemical analyzers. A digital biochip
                 manipulates liquids not as continuous flow, but as
                 discrete droplets on a two-dimensional array of
                 electrodes. Several electrodes are dynamically grouped
                 to form a virtual device, on which operations are
                 executed by moving the droplets. So far, researchers
                 have ignored the locations of droplets inside devices,
                 considering that all the electrodes forming the device
                 are occupied throughout the operation execution. In
                 this article, we consider a droplet-aware execution of
                 microfluidic operations, which means that we know the
                 exact position of droplets inside the modules at each
                 time-step. We propose a Tabu Search-based metaheuristic
                 for the synthesis of digital biochips with
                 droplet-aware operation execution. Experimental results
                 show that our approach can significantly reduce the
                 application completion time, allowing us to use smaller
                 area biochips and thus reduce costs.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Peper:2013:BCF,
  author =       "Ferdinand Peper and Jia Lee and Josep Carmona and
                 Jordi Cortadella and Kenichi Morita",
  title =        "{Brownian} Circuits: Fundamentals",
  journal =      j-JETC,
  volume =       "9",
  number =       "1",
  pages =        "3:1--3:??",
  month =        feb,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2422094.2422097",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Feb 20 16:42:57 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Random fluctuations will be a major factor interfering
                 with the operation of nanometer scale electronic
                 devices. This article presents circuit architectures
                 that can exploit such fluctuations, if signals have a
                 particle-like (discrete, token-based) character. We
                 define an abstract circuit primitive that, though
                 lacking functionality when used with fluctuation-free
                 signals, becomes universal when fluctuations are
                 allowed. Key to the power of a signal's fluctuations is
                 the ability to explore the state space of a circuit.
                 This ability is used to resolve deadlock situations,
                 which could otherwise only be averted by increased
                 design complexity. The results in this article suggest
                 that in the design of future computers, signal
                 fluctuations, rather than being an impediment to be
                 avoided at any cost, may be an important ingredient to
                 achieve efficient operation.",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Ghavami:2013:DAR,
  author =       "Behnam Ghavami and Mohsen Raji and Hossein Pedram and
                 Mehdi B. Tahoori",
  title =        "Design and Analysis of a Robust Carbon Nanotube-Based
                 Asynchronous Primitive Circuit",
  journal =      j-JETC,
  volume =       "9",
  number =       "1",
  pages =        "4:1--4:??",
  month =        feb,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2422094.2422098",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Feb 20 16:42:57 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Carbon Nanotube Field Effect Transistors (CNFETs) show
                 great promise as extensions to silicon CMOS. However,
                 CNFET-based circuits will face great fabrication
                 challenges that will translate into important parameter
                 variations and decreased reliability. Hence,
                 asynchronous logic, which is intrinsically more robust
                 to variability, seems an ideal and perhaps unavoidable
                 choice for digital circuits in CNFET technology. This
                 article presents the results on the design and analysis
                 of a CNFET-based implementation of an asynchronous
                 circuit primitive: the Muller C-element. Using a CNFET
                 SPICE model, we evaluate the robustness of CNFET-based
                 C-element in the presence of CNT fabrication-related
                 nonidealities. We investigate a quantitative evaluation
                 of how timing variability impacts the functionality of
                 a C-element and then, extract the necessary delay
                 constraints of the C-element circuit from the signal
                 transition graph specification. Considering the large
                 degrees of spatial correlation observed between the
                 CNFETs fabricated on directionally grown CNTs, a layout
                 technique is exploited to overcome the robustness
                 challenges of a CNFET-based C-element. Extensive Monte
                 Carlo simulations on the proposed technique have
                 demonstrated the effectiveness of the proposed
                 CNFET-based C-element by improving approximately 50X in
                 its robustness in expense of 65\% area, 47\% delay, and
                 56\% power consumption overheads. Experimental results
                 indicate that implementation of some CNFET-based Quasi
                 Delay Insensitive (QDI) benchmark circuits using the
                 proposed C-element results in significant robustness
                 improvement with negligible power and throughput
                 overheads. As a promising step toward CNFET-based
                 giga-scale integrated circuits, this article shows that
                 the asynchronous logic is an effective approach to
                 design robust integrated circuits in CNFET technology
                 with inherent extreme physical variations.",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chen:2013:SAR,
  author =       "Yung-Chih Chen and Soumya Eachempati and Chun-Yao Wang
                 and Suman Datta and Yuan Xie and Vijaykrishnan
                 Narayanan",
  title =        "A Synthesis Algorithm for Reconfigurable
                 Single-Electron Transistor Arrays",
  journal =      j-JETC,
  volume =       "9",
  number =       "1",
  pages =        "5:1--5:??",
  month =        feb,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2422094.2422099",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Feb 20 16:42:57 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Reducing power consumption has become one of the
                 primary challenges in chip design, and therefore
                 significant efforts are being devoted to find holistic
                 solutions on power reduction from the device level up
                 to the system level. Among a plethora of low power
                 devices that are being explored, single-electron
                 transistors (SETs) at room temperature are particularly
                 attractive. Although prior work has proposed a binary
                 decision diagram-based reconfigurable logic
                 architecture using SETs, it lacks an automatic
                 synthesis algorithm for the architecture. Consequently,
                 in this work, we develop a product-term-based approach
                 that synthesizes a logic circuit by mapping all its
                 product terms into the SET architecture. The
                 experimental results show the effectiveness and
                 efficiency of the proposed approach on a set of MCNC
                 benchmarks.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Tang:2013:TCT,
  author =       "Aoxiang Tang and Niraj K. Jha",
  title =        "Thermal Characterization of Test Techniques for
                 {FinFET} and {$3$D} Integrated Circuits",
  journal =      j-JETC,
  volume =       "9",
  number =       "1",
  pages =        "6:1--6:??",
  month =        feb,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2422094.2422100",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Feb 20 16:42:57 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Power consumption has become a very important
                 consideration during integrated circuit (IC) design and
                 test. During test, it can far exceed the values reached
                 during normal operation and, thus, lead to temperatures
                 above the allowed threshold. Without appropriate
                 temperature reduction, permanent damage may be caused
                 to the IC or invalid test results may be obtained.
                 FinFET is a double-gate field-effect transistor
                 (DG-FET) that was introduced commercially in 2012. Due
                 to the vertical nature of FinFETs and, hence, weaker
                 ability to dissipate heat, this problem is likely to
                 get worse for FinFET circuits. Another technology
                 rapidly gaining popularity is 3D IC integration.
                 Unfortunately, the compact nature of a multidie 3D IC
                 is likely to aggravate the temperature-during-test
                 problem even further. Hence, before temperature-aware
                 test methodologies can be developed, it is important to
                 thermally analyze both FinFET and 3D circuits under
                 test. In this article, we present a methodology for
                 thermal characterization of various test techniques,
                 such as scan and built-in self-test (BIST), for FinFET
                 and 3D ICs. FinFET thermal characterization makes use
                 of a FinFET standard cell library that is characterized
                 with the help of the University of Florida double-gate
                 (UFDG) SPICE model. Thermal profiles for circuits under
                 test are produced by ISAC2 from University of Colorado
                 for FinFET circuits and HotSpot from University of
                 Virginia for 3D ICs. Experimental results indicate that
                 high temperatures result under BIST and much less often
                 under scan, and that both power consumption and test
                 application time should be reduced to lower the
                 temperature of circuits under test, just reducing the
                 power consumption is not enough.",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Wang:2013:HRD,
  author =       "Shuo Wang and Jianwei Dai and Lei Wang",
  title =        "Hybrid Redundancy for Defect Tolerance in Molecular
                 Crossbar Memory",
  journal =      j-JETC,
  volume =       "9",
  number =       "1",
  pages =        "7:1--7:??",
  month =        feb,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2422094.2422101",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Feb 20 16:42:57 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Nano/molecular technologies have emerged as the
                 potential fabrics for building future integrated
                 systems. However, due to the imperfect fabrication
                 process, these extremely scaled devices are vulnerable
                 to a large number of defects and transient faults.
                 Memory systems, which are the primary application
                 targeted by these technologies, are particularly
                 exposed to this problem due to the ultra-high
                 integration density and elevated error sensitivity. In
                 this article, we propose a defect-tolerant technique,
                 referred to as hybrid redundancy allocation, for the
                 design of molecular crossbar memory systems. By using
                 soft redundancy (runtime exploitation of memory
                 spatial/temporal locality) in combination with hardware
                 redundancy (spare memory cells), the proposed technique
                 can achieve better error management at a low cost as
                 compared with conventional techniques. Simulation
                 results demonstrate the significant improvement in
                 defect tolerance, efficiency, and scalability of the
                 proposed technique.",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Narayanan:2013:VNF,
  author =       "Pritish Narayanan and Michael Leuchtenburg and Jorge
                 Kina and Prachi Joshi and Pavan Panchapakeshan and Chi
                 On Chui and C. Andras Moritz",
  title =        "Variability in Nanoscale Fabrics: Bottom-up Integrated
                 Analysis and Mitigation",
  journal =      j-JETC,
  volume =       "9",
  number =       "1",
  pages =        "8:1--8:??",
  month =        feb,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2422094.2422102",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Feb 20 16:42:57 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Emerging nanodevice-based architectures will be
                 impacted by parameter variation in conjunction with
                 high defect rates. Variations in key physical
                 parameters are caused by manufacturing imprecision as
                 well as fundamental atomic scale randomness. In this
                 article, the impact of parameter variation on nanoscale
                 computing fabrics is extensively studied through a
                 novel integrated methodology across device, circuit and
                 architectural levels. This integrated approach enables
                 to study in detail the impact of physical parameter
                 variation across all fabric layers. A final
                 contribution of the article includes novel techniques
                 to address this impact. The variability framework,
                 while generic, is explored extensively on the Nanoscale
                 Application Specific Integrated Circuits (NASICs)
                 nanowire fabric. For variation of $ \sigma = 10 $ in
                 key physical parameters, the on current is found to
                 vary by up to 3.5X. Circuit-level delay shows up to
                 118\% deviation from nominal. Monte Carlo simulations
                 using an architectural simulator found 67\%
                 nanoprocessor chips to operate below nominal
                 frequencies due to variation. New built-in variation
                 mitigation and fault-tolerance schemes, leveraging
                 redundancy, asymmetric delay paths and biased voting
                 schemes, were developed and evaluated to mitigate these
                 effects. They are shown to improve performance by up to
                 7.5X on a nanoscale processor design with variation,
                 and improve performance in designs relying on
                 redundancy for defect tolerance, without variation
                 assumed. Techniques show up to 3.8X improvement in
                 effective-yield performance products even at a high
                 12\% defect rate. The suite of techniques provides a
                 design space across key system-level metrics such as
                 performance, yield and area.",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Liang:2013:EWB,
  author =       "Jiale Liang and Stanley Yeh and S. Simon Wong and
                 H.-S. Philip Wong",
  title =        "Effect of Wordline\slash Bitline Scaling on the
                 Performance, Energy Consumption, and Reliability of
                 Cross-Point Memory Array",
  journal =      j-JETC,
  volume =       "9",
  number =       "1",
  pages =        "9:1--9:??",
  month =        feb,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2422094.2422103",
  ISSN =         "1550-4832 (print), 1550-4840 (electronic)",
  ISSN-L =       "1550-4832",
  bibdate =      "Wed Feb 20 16:42:57 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The impact of wordline/bitline metal wire scaling on
                 the write/read performance, energy consumption, speed,
                 and reliability of the cross-point memory array is
                 quantitatively studied for technology nodes down to
                 single-digit nm. The impending resistivity increase in
                 the Cu wires is found to cause significant decrease of
                 both write and read window margins at the regime when
                 electron surface scattering and grain boundary
                 scattering are substantial. At deeply-scaled device
                 dimensions, the wire energy dissipation and wire
                 latency become comparable to or even exceed the
                 intrinsic values of memory cells. The large current
                 density flowing through the wordlines/bitlines raises
                 additional reliability concerns for the cross-point
                 memory array. All these issues are exacerbated at
                 smaller memory resistance values and larger memory
                 array sizes. They thereby impose strict constraints on
                 the memory device design and preclude the realization
                 of large-scale cross-point memory array with minimum
                 feature sizes beyond the 10 nm node. A rethink in the
                 design methodology of cross-point memory to incorporate
                 and mitigate the scaling effects of wordline/bitline is
                 necessary. Possible solutions include the use of memory
                 wires with better conductivity and scalability, memory
                 arrays with smaller partition sizes, and memory
                 elements with larger resistance values and resistance
                 ratios.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Paul:2013:ISI,
  author =       "Bipul C. Paul and Arijit Raychowdhury",
  title =        "Introduction to the special issue on memory
                 technologies",
  journal =      j-JETC,
  volume =       "9",
  number =       "2",
  pages =        "10:1--10:??",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "1550-4832",
  bibdate =      "Sat Jun 1 11:19:09 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "10",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Yang:2013:MDC,
  author =       "J. Joshua Yang and R. Stanley Williams",
  title =        "Memristive devices in computing system: Promises and
                 challenges",
  journal =      j-JETC,
  volume =       "9",
  number =       "2",
  pages =        "11:1--11:??",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "1550-4832",
  bibdate =      "Sat Jun 1 11:19:09 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Memristive devices with a simple structure are not
                 only very small but also very versatile, which makes
                 them an ideal candidate used for the next generation
                 computing system in the post-Si era. The working
                 mechanism of the devices and a family of nanodevices
                 built based on this working mechanism are introduced
                 first followed by some proposed applications of these
                 novel devices. The promises and challenges of these
                 devices are then discussed, together with the
                 significant progresses made recently in dealing with
                 these challenges.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Jackson:2013:NES,
  author =       "Bryan L. Jackson and Bipin Rajendran and Gregory S.
                 Corrado and Matthew Breitwisch and Geoffrey W. Burr and
                 Roger Cheek and Kailash Gopalakrishnan and Simone Raoux
                 and Charles T. Rettner and Alvaro Padilla and Alex G.
                 Schrott and Rohit S. Shenoy and B{\"u}lent N. Kurdi and
                 Chung H. Lam and Dharmendra S. Modha",
  title =        "Nanoscale electronic synapses using phase change
                 devices",
  journal =      j-JETC,
  volume =       "9",
  number =       "2",
  pages =        "12:1--12:??",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "1550-4832",
  bibdate =      "Sat Jun 1 11:19:09 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The memory capacity, computational power,
                 communication bandwidth, energy consumption, and
                 physical size of the brain all tend to scale with the
                 number of synapses, which outnumber neurons by a factor
                 of 10,000. Although progress in cortical simulations
                 using modern digital computers has been rapid, the
                 essential disparity between the classical von Neumann
                 computer architecture and the computational fabric of
                 the nervous system makes large-scale simulations
                 expensive, power hungry, and time consuming. Over the
                 last three decades, CMOS-based neuromorphic
                 implementations of ``electronic cortex'' have emerged
                 as an energy efficient alternative for modeling
                 neuronal behavior. However, the key ingredient for
                 electronic implementation of any self-learning
                 system-programmable, plastic Hebbian synapses scalable
                 to biological densities-has remained elusive. We
                 demonstrate the viability of implementing such
                 electronic synapses using nanoscale phase change
                 devices. We introduce novel programming schemes for
                 modulation of device conductance to closely mimic the
                 phenomenon of Spike Timing Dependent Plasticity (STDP)
                 observed biologically, and verify through simulations
                 that such plastic phase change devices should support
                 simple correlative learning in networks of spiking
                 neurons. Our devices, when arranged in a crossbar array
                 architecture, could enable the development of
                 synaptronic systems that approach the density
                 (~10$^{11}$ synapses per sq cm) and energy efficiency
                 (consuming ~1pJ per synaptic programming event) of the
                 human brain.",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Apalkov:2013:STT,
  author =       "Dmytro Apalkov and Alexey Khvalkovskiy and Steven
                 Watts and Vladimir Nikitin and Xueti Tang and Daniel
                 Lottis and Kiseok Moon and Xiao Luo and Eugene Chen and
                 Adrian Ong and Alexander Driskill-Smith and Mohamad
                 Krounbi",
  title =        "Spin-transfer torque magnetic random access memory
                 {(STT-MRAM)}",
  journal =      j-JETC,
  volume =       "9",
  number =       "2",
  pages =        "13:1--13:??",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "1550-4832",
  bibdate =      "Sat Jun 1 11:19:09 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Spin-transfer torque magnetic random access memory
                 (STT-MRAM) is a novel, magnetic memory technology that
                 leverages the base platform established by an existing
                 100+nm node memory product called MRAM to enable a
                 scalable nonvolatile memory solution for advanced
                 process nodes. STT-MRAM features fast read and write
                 times, small cell sizes of 6F$^2$ and potentially even
                 smaller, and compatibility with existing DRAM and SRAM
                 architecture with relatively small associated cost
                 added. STT-MRAM is essentially a magnetic multilayer
                 resistive element cell that is fabricated as an
                 additional metal layer on top of conventional CMOS
                 access transistors. In this review we give an overview
                 of the existing STT-MRAM technologies currently in
                 research and development across the world, as well as
                 some specific discussion of results obtained at Grandis
                 and with our foundry partners. We will show that
                 in-plane STT-MRAM technology, particularly the DMTJ
                 design, is a mature technology that meets all
                 conventional requirements for an STT-MRAM cell to be a
                 nonvolatile solution matching DRAM and/or SRAM drive
                 circuitry. Exciting recent developments in
                 perpendicular STT-MRAM also indicate that this type of
                 STT-MRAM technology may reach maturity faster than
                 expected, allowing even smaller cell size and product
                 introduction at smaller nodes.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Mojumder:2013:DPS,
  author =       "Niladri N. Mojumder and Xuanyao Fong and Charles
                 Augustine and Sumeet K. Gupta and Sri Harsha Choday and
                 Kaushik Roy",
  title =        "Dual pillar spin-transfer torque {MRAMs} for low power
                 applications",
  journal =      j-JETC,
  volume =       "9",
  number =       "2",
  pages =        "14:1--14:??",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "1550-4832",
  bibdate =      "Sat Jun 1 11:19:09 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Electron-spin based data storage for on-chip memories
                 has the potential for ultra-high density, low power
                 consumption, very high endurance, and reasonably low
                 read/write latency. In this article, we discuss the
                 design challenges associated with spin-transfer torque
                 (STT) MRAM in its state-of-the-art configuration. We
                 propose an alternative bit cell configuration and three
                 new genres of magnetic tunnel junction (MTJ) structures
                 to improve STT-MRAM bit cell stabilities, write
                 endurance, and reduce write energy consumption. The
                 proposed multi-port, multi-pillar MTJ structures offer
                 the unique possibility of electrical and spatial
                 isolation of memory read and write. In order to realize
                 ultralow power under process variations, we propose
                 device, bit-cell and architecture level design
                 techniques. Such design alternatives at multiple levels
                 of design abstraction has been found to achieve
                 substantially enhanced robustness, density, reliability
                 and low power as compared to their charge-based
                 counterparts for future embedded applications.",
  acknowledgement = ack-nhfb,
  articleno =    "14",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chatterjee:2013:EAS,
  author =       "Subho Chatterjee and Sayeef Salahuddin and Satish
                 Kumar and Saibal Mukhopadhyay",
  title =        "Electrothermal analysis of spin-transfer-torque random
                 access memory arrays",
  journal =      j-JETC,
  volume =       "9",
  number =       "2",
  pages =        "15:1--15:??",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "1550-4832",
  bibdate =      "Sat Jun 1 11:19:09 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Spin Transfer Torque RAM (STTRAM) is a promising
                 candidate for fast, scalable, high-density, nonvolatile
                 memory in nanometer technology. However, relatively
                 high write current density and small volume of the
                 memory device indicate the possibility of significant
                 self-heating in the STTRAM structure. This article
                 performs a critical analysis of the self-heating
                 induced temperature variations in STTRAM. We perform a
                 3D finite volume method based study to characterize
                 self-heating effect in a single cell. The analysis is
                 extended for STTRAM arrays by developing a
                 computationally efficient RC compact model based
                 thermal analyzer. The analysis shows that self-heating
                 can results in considerable increase in both
                 steady-state value and transient change in temperature
                 of individual cells. The effect is less pronounced at
                 the array level and depends on the activity level, that
                 is, number of active cells within an array size. The
                 analysis further illustrates that self-heating
                 negatively impacts electrical reliability metrics
                 namely, read margin and detection accuracy; degrades
                 cell performance; and modulates energy dissipation.",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chen:2013:CCB,
  author =       "Yiran Chen and Weng-Fai Wong and Hai Li and Cheng-Kok
                 Koh and Yaojun Zhang and Wujie Wen",
  title =        "On-chip caches built on multilevel spin-transfer
                 torque {RAM} cells and its optimizations",
  journal =      j-JETC,
  volume =       "9",
  number =       "2",
  pages =        "16:1--16:??",
  month =        may,
  year =         "2013",
  CODEN =        "????",
  ISSN =         "1550-4832",
  bibdate =      "Sat Jun 1 11:19:09 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "It has been predicted that a processor's caches could
                 occupy as much as 90\% of chip area a few technology
                 nodes from the current ones. In this article, we
                 investigate the use of multilevel spin-transfer torque
                 RAM (STT-RAM) cells in the design of processor caches.
                 We start with examining the access (read and write)
                 scheme for multilevel cell (MLC) STT-RAM from a circuit
                 design perspective, detailing the read and write
                 circuits. Compared to traditional SRAM caches, a
                 multilevel cell (MLC) STT-RAM cache design is denser,
                 fast, and requires less energy. However, a number of
                 critical architecture-level issues remain to be solved
                 before MLC STT-RAM technology can be deployed in
                 processor caches. We shall offer solutions to the issue
                 of bit encoding as well as tackle the write endurance
                 problem. In particular, the latter has been neglected
                 in previous works on STT-RAM caches. We propose a set
                 remapping scheme that can potentially prolong the
                 lifetime of a MLC STT-RAM cache by 80$ \times $ on
                 average. Furthermore, a method for recovering the
                 performance that may be lost in some applications due
                 to set remapping is proposed. The impacts of process
                 variations of the MLC STT-RAM cell on the robustness of
                 the memory hierarchy is also discussed, together with
                 various enhancement techniques, namely, ECC and design
                 redundancy.",
  acknowledgement = ack-nhfb,
  articleno =    "16",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Thapliyal:2013:DER,
  author =       "Himanshu Thapliyal and Nagarajan Ranganathan",
  title =        "Design of efficient reversible logic-based binary and
                 {BCD} adder circuits",
  journal =      j-JETC,
  volume =       "9",
  number =       "3",
  pages =        "17:1--17:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2491682",
  ISSN =         "1550-4832",
  bibdate =      "Tue Oct 1 18:20:25 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Reversible logic is gaining significance in the
                 context of emerging technologies such as quantum
                 computing since reversible circuits do not lose
                 information during computation and there is one-to-one
                 mapping between the inputs and outputs. In this work,
                 we present a class of new designs for reversible binary
                 and BCD adder circuits. The proposed designs are
                 primarily optimized for the number of ancilla inputs
                 and the number of garbage outputs and are designed for
                 possible best values for the quantum cost and delay. In
                 reversible circuits, in addition to the primary inputs,
                 some constant input bits are used to realize different
                 logic functions which are referred to as ancilla inputs
                 and are overheads that need to be reduced. Further, the
                 garbage outputs which do not contribute to any useful
                 computations but are needed to maintain reversibility
                 are also overheads that need to be reduced in
                 reversible designs. First, we propose two new designs
                 for the reversible ripple carry adder: (i) one with no
                 input carry$c_0$ and no ancilla input bits, and (ii)
                 one with input carry$c_0$ and no ancilla input bits.
                 The proposed reversible ripple carry adder designs with
                 no ancilla input bits have less quantum cost and logic
                 depth (delay) compared to their existing counterparts
                 in the literature. In these designs, the quantum cost
                 and delay are reduced by deriving designs based on the
                 reversible Peres gate and the TR gate. Next, four new
                 designs for the reversible BCD adder are presented
                 based on the following two approaches: (i) the addition
                 is performed in binary mode and correction is applied
                 to convert to BCD when required through detection and
                 correction, and (ii) the addition is performed in
                 binary mode and the result is always converted using a
                 binary to BCD converter. The proposed reversible binary
                 and BCD adders can be applied in a wide variety of
                 digital signal processing applications and constitute
                 important design components of reversible computing.",
  acknowledgement = ack-nhfb,
  articleno =    "17",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Lee:2013:CIP,
  author =       "Woo Hyung Lee and Pinaki Mazumder",
  title =        "Color image processing with multi-peak resonant
                 tunneling diodes",
  journal =      j-JETC,
  volume =       "9",
  number =       "3",
  pages =        "18:1--18:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2503128",
  ISSN =         "1550-4832",
  bibdate =      "Tue Oct 1 18:20:25 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The article introduces a novel approach to color image
                 processing that utilizes multi-peak resonant tunneling
                 diodes for encoding color information in quantized
                 states of the diodes. The Multi-Peak Resonant Tunneling
                 Diodes (MPRTDs) are organized as a two-dimensional
                 array of vertical pillars which are locally connected
                 by programmable passive and active elements with a view
                 to realizing a wide variety of color image processing
                 functions such as quantization, color extraction, image
                 smoothing, edge detection, and line detection. In order
                 to process color information in the input images, two
                 different methods for color representation schemes have
                 been used: one using color mapping and the other using
                 direct RGB representation. Finally, the article uses
                 HSPICE simulation methods for the nestlist of the
                 proposed RTD-based nanoarchitecture in order to verify
                 a candidate of image functions by using the
                 afore-mentioned representation methods.",
  acknowledgement = ack-nhfb,
  articleno =    "18",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Bobba:2013:CTP,
  author =       "Shashikanth Bobba and Ashutosh Chakraborty and Olivier
                 Thomas and Perrine Batude and Giovanni de Micheli",
  title =        "Cell transformations and physical design techniques
                 for {$3$D} monolithic integrated circuits",
  journal =      j-JETC,
  volume =       "9",
  number =       "3",
  pages =        "19:1--19:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2491675",
  ISSN =         "1550-4832",
  bibdate =      "Tue Oct 1 18:20:25 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "3D Monolithic Integration (3DMI), also termed as
                 sequential integration, is a potential technology for
                 future gigascale circuits. In 3DMI technology the 3D
                 contacts, connecting different active layers, are in
                 the order of few 100nm. Given the advantage of such
                 small contacts, 3DMI enables fine-grain (gate-level)
                 partitioning of circuits. In this work we present three
                 cell transformation techniques for standard cell-based
                 ICs with 3DMI technology. As a major contribution of
                 this work, we propose a design flow comprising of a
                 cell transformation technique, cell-on-cell stacking,
                 and a physical design technique ({CELONCEL$_{PD}$} )
                 aimed at placing cells transformed with cell-on-cell
                 stacking. We analyze and compare various cell
                 transformation techniques for 3DMI technology without
                 disrupting the regularity of the IC design flow. Our
                 experiments demonstrate the effectiveness of CELONCEL
                 design technique, yielding us an area reduction of
                 37.5\%, 16.2\% average reduction in wirelength, and
                 6.2\% average improvement in overall delay, compared
                 with a 2D case when benchmarked across various designs
                 in 45nm technology node.",
  acknowledgement = ack-nhfb,
  articleno =    "19",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Tang:2013:DSE,
  author =       "Aoxiang Tang and Niraj K. Jha",
  title =        "Design space exploration of {FinFET} cache",
  journal =      j-JETC,
  volume =       "9",
  number =       "3",
  pages =        "20:1--20:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2491678",
  ISSN =         "1550-4832",
  bibdate =      "Tue Oct 1 18:20:25 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Integration of cache on-chip has significantly
                 improved the performance of modern processors. The
                 relentless demand for ever-increasing performance has
                 led to the need to increase the cache capacity and
                 number of cache levels. However, the performance
                 improvement is accompanied by an increase in chip's
                 power dissipation, requiring the use of more expensive
                 cooling technologies to ensure chip reliability and
                 long product life. The emergence of FinFETs as the
                 technology of choice for high-performance computing
                 poses new challenges to processor designers. With the
                 introduction of new features in FinFETs, for example,
                 independently controllable back gates, researchers have
                 proposed several innovative memory cells that can
                 reduce leakage power significantly, making the
                 integration of a larger cache more practical. In this
                 article, we comprehensively evaluate and compare the
                 performance, power consumption (both dynamic and
                 leakage), area, and temperature of different FinFET
                 SRAM caches by exploring common configurations with
                 varying cache size, block size, associativity, and
                 number of banks. We evaluate caches based on four
                 well-known FinFET SRAM cells: Pass-Gate FeedBack
                 (PGFB), Row-based Back-Gate Biasing (RBGB), 8T, and 4T.
                 We show how the caches can be simulated at
                 self-consistent temperatures (at which leakage and
                 temperature are in equilibrium). Drowsy and decay
                 caches are two well-known leakage reduction techniques.
                 We implement them in the context of FinFET caches to
                 investigate their impact. We show that the RBGB
                 cell-based cache is far superior in leakage and
                 Power-Delay Product (PDP) to those based on the other
                 three cells, sometimes by an order of magnitude. This
                 superiority is maintained even when drowsy or decay
                 leakage reduction techniques are applied to caches
                 based on the other three cells, but not to the one
                 based on the RBGB cell. This significantly diminishes
                 the importance of drowsy or decay cache techniques, at
                 least when the RBGB cell is used.",
  acknowledgement = ack-nhfb,
  articleno =    "20",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Zamani:2013:IFV,
  author =       "Masoud Zamani and Hanieh Mirzaei and Mehdi B.
                 Tahoori",
  title =        "{ILP} formulations for variation\slash defect-tolerant
                 logic mapping on crossbar nano-architectures",
  journal =      j-JETC,
  volume =       "9",
  number =       "3",
  pages =        "21:1--21:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2491680",
  ISSN =         "1550-4832",
  bibdate =      "Tue Oct 1 18:20:25 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Several emerging nano-technologies, including crossbar
                 nano-architectures, have recently been studied as
                 possible replacement or supplement to CMOS technology
                 in the future. However, extreme process variation and
                 high failure rates, mainly due to atomic device sizes,
                 are major challenges for crossbar nano-architectures.
                 This article presents variation- and defect-tolerant
                 logic mapping on crossbar nano-architectures. Since
                 variation/defect-aware mapping is an NP-hard problem,
                 we introduce a set of Integer Linear Programming (ILP)
                 formulations to effectively solve the problem in a
                 reasonable time. The proposed ILP formulations can be
                 used for both diode-based and FET-based crossbars.
                 Experimental results on benchmark circuits show that
                 our approach can reduce the critical-path delay 39\%
                 compared to the Simulated Annealing (SA) method. It can
                 also successfully achieve 97\% defect-free mapping with
                 40\% defect density. It can tolerate process variations
                 to meet timing constraints in 95\% of the cases,
                 compared to only 77\% achieved by SA.",
  acknowledgement = ack-nhfb,
  articleno =    "21",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Sun:2013:EVC,
  author =       "Guangyu Sun and Eren Kursun and Jude A. Rivers and
                 Yuan Xie",
  title =        "Exploring the vulnerability of {CMPs} to soft errors
                 with {$3$D} stacked nonvolatile memory",
  journal =      j-JETC,
  volume =       "9",
  number =       "3",
  pages =        "22:1--22:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2491679",
  ISSN =         "1550-4832",
  bibdate =      "Tue Oct 1 18:20:25 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Improving the vulnerability to soft errors is one of
                 the important design goals for future architecture
                 design of Chip-MultiProcessors (CMPs). In this study,
                 we explore the soft error characteristics of CMPs with
                 3D stacked NonVolatile Memory (NVM), in particular, the
                 Spin-Transfer Torque Random Access Memory (STT-RAM),
                 whose cells are immune to radiation-induced soft errors
                 and do not have endurance problems. We use 3D stacking
                 as an enabler for modular integration of STT-RAM
                 memories with minimum disruption in the baseline
                 processor design flow, while providing further
                 interconnection and capacity advantages. We take an
                 in-depth look at alternative replacement schemes to
                 explore the soft error resilience benefits and design
                 trade-offs of 3D stacked STT-RAM and capture the
                 multivariable optimization challenges microprocessor
                 architectures face. We propose a vulnerability metric,
                 with respect to the instruction and data in the core
                 pipeline and through the cache hierarchy, to present a
                 comprehensive system evaluation with respect to
                 reliability, performance, and power consumption for our
                 CMP architectures. Our experimental results show that,
                 for the average workload, replacing memories with an
                 STT-RAM alternative significantly mitigates soft errors
                 on-chip, improves the performance by 14.15\%, and
                 reduces power consumption by 13.44\%.",
  acknowledgement = ack-nhfb,
  articleno =    "22",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Yang:2013:NAC,
  author =       "Shengqi Yang and Wenping Wang and Mark Hagan and Wei
                 Zhang and Pallav Gupta and Yu Cao",
  title =        "{NBTI}-aware circuit node criticality computation",
  journal =      j-JETC,
  volume =       "9",
  number =       "3",
  pages =        "23:1--23:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2491681",
  ISSN =         "1550-4832",
  bibdate =      "Tue Oct 1 18:20:25 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "For sub-65nm technology nodes, Negative Bias
                 Temperature Instability (NBTI) has become a primary
                 limiting factor of circuit lifetime. During the past
                 few years, researchers have spent considerable effort
                 on accurate modeling and characterization of circuit
                 delay degradation caused by NBTI at different design
                 levels. The search for techniques and methodologies
                 which can aid in effectively minimizing the NBTI effect
                 on circuit delay is still underway. In this work, we
                 present the usage of node criticality computation to
                 drive NBTI-aware timing analysis and optimization.
                 Circuits that have undergone this optimization flow
                 show strong resistance to NBTI delay degradation. For
                 the first time, this work proposes a node criticality
                 computation algorithm under an NBTI-aware timing
                 analysis and optimization framework. Our work provides
                 answers to the following yet unaddressed questions: (a)
                 what is the definition of node criticality in a circuit
                 under the NBTI effect? (b) how do we identify the
                 critical nodes that, once protected, will be immune to
                 NBTI timing degradation? and (c) what are the NBTI
                 effect attenuation approaches? Experimental results
                 indicate that by protecting the critical nodes found by
                 our proposed methodology, circuit delay degradation can
                 be reduced by up to 50\%. Combined with peak
                 temperature reduction, the delay degradation can be be
                 further improved.",
  acknowledgement = ack-nhfb,
  articleno =    "23",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Wettin:2013:CNE,
  author =       "Paul Wettin and Anuroop Vidapalapati and Amlan Gangul
                 and Partha Pratim Pande",
  title =        "Complex network-enabled robust wireless
                 network-on-chip architectures",
  journal =      j-JETC,
  volume =       "9",
  number =       "3",
  pages =        "24:1--24:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2491676",
  ISSN =         "1550-4832",
  bibdate =      "Tue Oct 1 18:20:25 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The Network-on-Chip (NoC) paradigm has emerged as a
                 scalable interconnection infrastructure for modern
                 multicore chips. However, with growing levels of
                 integration, the traditional NoCs suffer from high
                 latency and energy dissipation in on-chip data transfer
                 due to conventional multihop metal/dielectric-based
                 interconnects. Three-dimensional integration, on-chip
                 photonics, RF, and wireless links have been proposed as
                 radical low-power and low-latency alternatives to the
                 conventional planar wire-based designs. Wireless NoCs
                 with Carbon NanoTube (CNT) antennas are shown to
                 outperform traditional wire-based NoCs significantly in
                 achievable data rate and energy dissipation. However,
                 such emerging and transformative technologies will be
                 prone to high levels of failures due to various issues
                 related to manufacturing challenges and integration. On
                 the other hand, several naturally occurring complex
                 networks such as colonies of microbes and the World
                 Wide Web are known to be inherently robust against high
                 rates of failures and harsh environments. This article
                 advocates adoption of such complex network-based
                 architectures to minimize the effect of wireless link
                 failures on the performance of the NoC. Through
                 cycle-accurate simulations it is shown that the
                 wireless NoC architectures inspired by natural complex
                 networks perform better than their conventional wired
                 counterparts even in the presence of high degrees of
                 link failures. We demonstrate the robustness of the
                 proposed wireless NoC architecture by incorporating
                 both uniform and application-specific traffic
                 patterns.",
  acknowledgement = ack-nhfb,
  articleno =    "24",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Zhang:2013:DTU,
  author =       "Xuehui Zhang and Andrew Ferraiuolo and Mohammad
                 Tehranipoor",
  title =        "Detection of trojans using a combined ring oscillator
                 network and off-chip transient power analysis",
  journal =      j-JETC,
  volume =       "9",
  number =       "3",
  pages =        "25:1--25:??",
  month =        sep,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2491677",
  ISSN =         "1550-4832",
  bibdate =      "Tue Oct 1 18:20:25 MDT 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Verifying the trustworthiness of Integrated Circuits
                 (ICs) is of utmost importance, as hardware Trojans may
                 destroy ICs bound for critical applications. A novel
                 methodology combining on-chip structure with external
                 current measurements is proposed to verify whether or
                 not an IC is Trojan free. This method considers
                 Trojans' impact on neighboring cells and on the entire
                 IC's power consumption, and effectively localizes the
                 measurement of dynamic power. To achieve this, we
                 develop a new on-chip ring oscillator network structure
                 distributed across the entire chip and place each ring
                 oscillator's components in different rows of a
                 standard-cell design. By developing novel statistical
                 data analysis, the effect of process variations on the
                 ICs' transient power will be separated from the effect
                 of Trojans. Simulation results using 90nm technology
                 and experimental results on Xilinx Spartan-6 FPGAs
                 demonstrate the efficiency of our proposed method.",
  acknowledgement = ack-nhfb,
  articleno =    "25",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Guiducci:2013:ISI,
  author =       "Carlotta Guiducci",
  title =        "Introduction to Special Issue on Bioinformatics",
  journal =      j-JETC,
  volume =       "9",
  number =       "4",
  pages =        "26:1--26:??",
  month =        nov,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2536744.2536745",
  ISSN =         "1550-4832",
  bibdate =      "Wed Nov 27 17:50:48 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "26",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Piovesan:2013:ERP,
  author =       "Damiano Piovesan and Giuseppe Profiti and Pier Luigi
                 Martelli and Piero Fariselli and Rita Casadio",
  title =        "Extended and Robust Protein Sequence Annotation over
                 Conservative Nonhierarchical Clusters: The Case Study
                 of the {ABC} Transporters",
  journal =      j-JETC,
  volume =       "9",
  number =       "4",
  pages =        "27:1--27:??",
  month =        nov,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2504729",
  ISSN =         "1550-4832",
  bibdate =      "Wed Nov 27 17:50:48 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Genome annotation is one of the most important issues
                 in the genomic era. The exponential growth rate of
                 newly sequenced genomes and proteomes urges the
                 development of fast and reliable annotation methods,
                 suited to exploit all the information available in
                 curated databases of protein sequences and structures.
                 To this aim we developed BAR+, the Bologna Annotation
                 Resource. The basic notion is that sequences with high
                 identity value to a counterpart can inherit the same
                 function/s and structure, if available. As a case study
                 we describe how the ATP-binding domain of the ABC
                 transporters can be found and modeled in over 30,000
                 new sequences not annotated before. We also mapped into
                 BAR+ all the ABC transporters listed in the Transporter
                 Classification DataBase and found that within our
                 environment annotation could be extended to another
                 256,866 sequences.",
  acknowledgement = ack-nhfb,
  articleno =    "27",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Abate:2013:ILH,
  author =       "Francesco Abate and Andrea Acquaviva and Elisa Ficarra
                 and Enrico Macii",
  title =        "Integration of Literature with Heterogeneous
                 Information for Genes Correlation Scoring",
  journal =      j-JETC,
  volume =       "9",
  number =       "4",
  pages =        "28:1--28:??",
  month =        nov,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2504728",
  ISSN =         "1550-4832",
  bibdate =      "Wed Nov 27 17:50:48 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Determining the correlation between biomedical terms
                 is a powerful instrument to help scientist research
                 activity, both to understand experimental results and
                 to design new ones. In particular, a great potential
                 comes from the integration of the many heterogeneous
                 information sources currently available on the Web. In
                 this article we focus on the correlation between genes
                 and biological processes. In this context, we present a
                 methodology for integrating information from biomedical
                 literature with other heterogeneous types of structured
                 information. In particular, the information sources
                 integrated in this work are PubMed abstracts, pathway
                 databases, and NCI thesaurus definitions. The
                 integration is performed at the semantic analysis level
                 using a customized approach we developed to modulate
                 the impact of the different sources on the correlation
                 score. We report the results of a study concerning the
                 impact of the information integration on the
                 correlation score and of the user-level parameters we
                 introduced to modulate the impact of pathway data or
                 NCI definitions with respect to biomedical literature
                 information, depending on the context of the search. To
                 evaluate the methodology, we performed correlation
                 measures on six biological processes and nine genes by
                 comparing the results with and without the integration
                 of pathways and NCI definitions.",
  acknowledgement = ack-nhfb,
  articleno =    "28",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Graziano:2013:HVB,
  author =       "Mariagrazia Graziano and Stefano Frache and Maurizio
                 Zamboni",
  title =        "A Hardware Viewpoint on Biosequence Analysis: What's
                 Next?",
  journal =      j-JETC,
  volume =       "9",
  number =       "4",
  pages =        "29:1--29:??",
  month =        nov,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2504774",
  ISSN =         "1550-4832",
  bibdate =      "Wed Nov 27 17:50:48 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Biosequence alignment recently received an increasing
                 support from both commodity and dedicated hardware
                 platforms. Processing capabilities are constantly
                 rising, but still not satisfying the limitless
                 requirements of this application. We give an insight on
                 the contribution to this need that can possibly be
                 expected from emerging technology devices and
                 architectures, focusing as an example on nanofabrics
                 based on silicon nanowires. By varying a few parameters
                 we explore the solution space, and demonstrate with
                 proper figures of merit how this family of beyond CMOS
                 structures could be considered as the effective
                 disruptive technology for biosequence analysis
                 applications.",
  acknowledgement = ack-nhfb,
  articleno =    "29",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Venken:2013:SBM,
  author =       "Lyn Venken and Kathleen Marchal and Jos Vanderleyden",
  title =        "Synthetic Biology and Microdevices: a Powerful
                 Combination",
  journal =      j-JETC,
  volume =       "9",
  number =       "4",
  pages =        "30:1--30:??",
  month =        nov,
  year =         "2013",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2504775",
  ISSN =         "1550-4832",
  bibdate =      "Wed Nov 27 17:50:48 MST 2013",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Recent developments demonstrate that the combination
                 of microbiology with micro- and nanoelectronics is a
                 successful approach to develop new miniaturized sensing
                 devices and other technologies. In the last decade,
                 there has been a shift from the optimization of the
                 abiotic components, for example, the chip, to the
                 improvement of the processing capabilities of cells
                 through genetic engineering. The synthetic biology
                 approach will not only give rise to systems with new
                 functionalities, but will also improve the robustness
                 and speed of their response towards applied signals. To
                 this end, the development of new genetic circuits has
                 to be guided by computational design methods that
                 enable to tune and optimize the circuit response. As
                 the successful design of genetic circuits is highly
                 dependent on the quality and reliability of its
                 composing elements, intense characterization of
                 standard biological parts will be crucial for an
                 efficient rational design process in the development of
                 new genetic circuits. Microengineered devices can
                 thereby offer a new analytical approach for the study
                 of complex biological parts and systems. By summarizing
                 the recent techniques in creating new synthetic
                 circuits and in integrating biology with microdevices,
                 this review aims at emphasizing the power of combining
                 synthetic biology with microfluidics and
                 microelectronics.",
  acknowledgement = ack-nhfb,
  articleno =    "30",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Editors:2014:ISI,
  author =       "Editors",
  title =        "Introduction to special issue on reliability and
                 device degradation in emerging technologies",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "1:1--1:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2543749.2543750",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "1",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Kufluoglu:2014:RMN,
  author =       "Haldun K{\"u}fl{\"u}oglu and Cathy Chancellor and Min
                 Chen and Claude Cirba and Vijay Reddy",
  title =        "Recovery modeling of negative bias temperature
                 instability {(NBTI)} for {SPICE}-compatible circuit
                 aging simulators",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "2:1--2:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2517648",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "A feasible computational framework that enables
                 improved predictability of NBTI degradation within
                 commercially available tools is discussed. The NBTI
                 model is used for real-time circuit operation where
                 recovery is present. The complementary nature of
                 implementation is readily incorporated into existing
                 model extraction and verification tools. The method
                 provides significantly enhanced accuracy in simulations
                 when compared to circuit data, yet retains practicality
                 and flexibility.",
  acknowledgement = ack-nhfb,
  articleno =    "2",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Arasu:2014:RIL,
  author =       "Senthil Arasu and Mehrdad Nourani and Vijay Reddy and
                 John M. {Carulli Jr.} and Gautam Kapila and Min Chen",
  title =        "Reliability improvement of logic and clock paths in
                 power-efficient designs",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "3:1--3:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2543749.2543751",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Performance degradation due to transistor aging is a
                 significant impediment to high-performance IC design
                 due to increasing concerns of reliability mechanisms
                 such as negative-bias-temperature-instability (NBTI).
                 The concern only grows with technology scaling as the
                 effects of positive bias temperature instability (PBTI)
                 is becoming prominent in future technologies and
                 compounding with the effects of NBTI. Although aging of
                 transistor is inevitable and the magnitude of
                 degradation due to aging varies depending upon the
                 context. Specifically, in power-efficient systems
                 designs, the logic and clock paths are susceptible to
                 static stress resulting in peak degradation due to BTI
                 occurrence when clock is gated. In this article, we
                 present the reliability impact of making systems power
                 efficient and propose a design-for-reliability
                 methodology that can be used in conjunction with
                 low-power design techniques to alleviate the stress
                 conditions caused by rendering circuits in idle state.
                 The technique- BTI-Refresh, is shown to be applicable
                 to both logic and clock paths alike and focuses on
                 preventing prolonged static stress using periodic
                 refreshes to achieve alternating stress. The mechanism
                 is shown to integrate seamlessly into the design at
                 gate-level without requiring any architectural or
                 RT-level changes. Using ISCAS benchmarks and
                 Kogge-Stone-Adder circuits, it is shown to reduce the
                 aging effect in logic path delay due to static stress
                 by up to 50\% with negligible area and power overhead.
                 BTI-Refresh is extended to clock-paths to prevent
                 pulse-width degradation due to static aging and with
                 minimal clock-skew.",
  acknowledgement = ack-nhfb,
  articleno =    "3",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Sun:2014:WAC,
  author =       "Jin Sun and Roman Lysecky and Karthik Shankar and
                 Avinash Kodi and Ahmed Louri and Janet Roveda",
  title =        "Workload assignment considering {NBTI} degradation in
                 multicore systems",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "4:1--4:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2539124",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "With continuously shrinking technology, reliability
                 issues such as Negative Bias Temperature Instability
                 (NBTI) has resulted in considerable degradation of
                 device performance, and eventually the short
                 mean-time-to-failure (MTTF) of the whole multicore
                 system. This article proposes a new workload balancing
                 scheme based on device-level fractional NBTI model to
                 balance the workload among active cores while relaxing
                 stressed ones. Starting with NBTI-induced threshold
                 voltage degradation, we define a concept of Capacity
                 Rate (CR) as an indication of one core's ability to
                 accept workload. Capacity rate captures core's
                 performance variability in terms of delay and power
                 metrics under the impact of NBTI aging. The proposed
                 workload balancing framework employs the capacity rates
                 as workload constraints, applies a Dynamic Zoning (DZ)
                 algorithm to group cores into zones to process task
                 flows, and then uses Dynamic Task Scheduling (DTS) to
                 allocate tasks in each zone with balanced workload and
                 minimum communication cost. Experimental results on a
                 64-core system show that by allowing a small part of
                 the cores to relax over a short time period, the
                 proposed methodology improves multicore system yield
                 (percentage of core failures) by 20\%, while extending
                 MTTF by 30\% with insignificant degradation in
                 performance (less than 3\%).",
  acknowledgement = ack-nhfb,
  articleno =    "4",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chabi:2014:RLA,
  author =       "Djaafar Chabi and Damien Querlioz and Weisheng Zhao
                 and Jacques-Olivier Klein",
  title =        "Robust learning approach for neuro-inspired nanoscale
                 crossbar architecture",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "5:1--5:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2539123",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Scaling beyond CMOS require a new combination of
                 computing paradigm and new devices. In this context,
                 memristor are often considered as best candidate to
                 implement efficiently synapses in hardware neural
                 networks. In this article, we analyze the impact of
                 memristor parameter variability. We build an analytical
                 model of the global reliability at the crossbar level.
                 It is based on a supervised learning method with
                 multilayer and redundancy extensions. Comparisons with
                 Monte Carlo simulations of small neural network
                 validate our analytical model. It can be used to
                 extrapolate directly the reliability of large-scale
                 neural system. Our extrapolations show that high defect
                 rate and important parameter variability can be handle
                 efficiency with a moderate amount of redundancy.",
  acknowledgement = ack-nhfb,
  articleno =    "5",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Frache:2014:NAM,
  author =       "Stefano Frache and Mariagrazia Graziano and Maurizio
                 Zamboni",
  title =        "Nanoarray architectures multilevel simulation",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "6:1--6:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2541882",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Density and regularity are deemed as the major
                 advantages of nanoarray architectures based on
                 nanowires. Literature demonstrated that proper
                 reliability analyzes must be performed and solutions
                 have to be devised to improve nanoarrays yield. Their
                 complexity and high-fault probability claim for
                 specific design automation tools able to explore
                 circuit solutions, performance and fault-tolerant
                 approaches. We envision a simulator conceived to carry
                 on characterizations in terms of logic behavior,
                 defect-induced output error rate assessment, switching
                 activity, power and timing performance. Though already
                 existing for traditional technology, a simulator based
                 on specific technological and topological tiled
                 nanoarray descriptions, and conceived to join both
                 device and architecture levels, has never been
                 attempted at the degree of accuracy we present. Our
                 contribution is twofold. First, marking a difference
                 with respect to the state of the art, we developed an
                 algorithm based on an event-driven engine which works
                 at switch level and is not simply built on top of cost
                 functions evaluations. The straightforward advantage is
                 the possibility to follow the evolution of dynamic
                 control sequences throughout all the inner components
                 of the nanoarray, and, as a consequence, to obtain
                 circuit level characterization as a projection of the
                 real internal parameters. Second, we added to our
                 simulator the capability to inject faults with specific
                 statistical distributions associated to the nanoarray
                 topology. Here we extract output error rates and yield
                 for one of the possible nanoarray structures proposed
                 in literature, the NASIC. Results specificity and
                 accuracy demonstrate the simulator trustworthiness, its
                 effectiveness for extensive nanoarrays characterization
                 and its suitability as a foundation for both higher
                 architectural and lower device simulation levels. The
                 aim of this work, then, is to provide insights into the
                 intertwined relation between actual technology and
                 circuit design for these emerging fabrics, and, as a
                 consequence, to clarify how defects and variability
                 affect circuits and systems performance.",
  acknowledgement = ack-nhfb,
  articleno =    "6",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Avritzer:2014:ISI,
  author =       "Alberto Avritzer and Tadashi Dohi",
  title =        "Introduction to special issue on {WoSAR 2011}",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "7:1--7:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2543749.2543752",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  acknowledgement = ack-nhfb,
  articleno =    "7",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Cotroneo:2014:SSA,
  author =       "Domenico Cotroneo and Roberto Natella and Roberto
                 Pietrantuono and Stefano Russo",
  title =        "A survey of software aging and rejuvenation studies",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "8:1--8:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2539117",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Software aging is a phenomenon plaguing many
                 long-running complex software systems, which exhibit
                 performance degradation or an increasing failure rate.
                 Several strategies based on the proactive rejuvenation
                 of the software state have been proposed to counteract
                 software aging and prevent failures. This survey
                 article provides an overview of studies on Software
                 Aging and Rejuvenation (SAR) that have appeared in
                 major journals and conference proceedings, with respect
                 to the statistical approaches that have been used to
                 forecast software aging phenomena and to plan
                 rejuvenation, the kind of systems and aging effects
                 that have been studied, and the techniques that have
                 been proposed to rejuvenate complex software systems.
                 The analysis is useful to identify key results from SAR
                 research, and it is leveraged in this article to
                 highlight trends and open issues.",
  acknowledgement = ack-nhfb,
  articleno =    "8",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Zhao:2014:SRS,
  author =       "Jing Zhao and Yuliang Jin and Kishor S. Trivedi and
                 Rivalino {Matias Jr.} and Yanbin Wang",
  title =        "Software rejuvenation scheduling using accelerated
                 life testing",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "9:1--9:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2539118",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "A number of studies have reported the phenomenon of
                 ``Software aging'', caused by resource exhaustion and
                 characterized by progressive software performance
                 degradation. In this article, we carry out an
                 experimental study of software aging and rejuvenation
                 for an on-line bookstore application, following the
                 standard configuration of TPC-W benchmark. While real
                 website is used for the bookstore, the clients are
                 emulated. In order to reduce the time to application
                 failures caused by memory leaks, we use the accelerated
                 life testing (ALT) approach. We then select the Weibull
                 time to failure distribution at normal level, to be
                 used in a semi-Markov process, to compute the optimal
                 software rejuvenation trigger interval. Since the
                 validation of optimal rejuvenation trigger interval
                 with emulated browsers will take an inordinate long
                 time, we develop a simulation model to validate the ALT
                 experimental results, and also estimate the
                 steady-state availability to cross-validate the results
                 of the semi-Markov availability model.",
  acknowledgement = ack-nhfb,
  articleno =    "9",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Machida:2014:JCT,
  author =       "Fumio Machida and Victor F. Nicola and Kishor S.
                 Trivedi",
  title =        "Job completion time on a virtualized server with
                 software rejuvenation",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "10:1--10:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2539121",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "This article analyzes the completion time of a job
                 running on a virtualized server subject to software
                 aging and rejuvenation in a virtual machine monitor
                 (VMM). A job running on the server may be interrupted
                 by virtual machine (VM) failure, VMM failure or VMM
                 rejuvenation. The job interruption is categorized as
                 either preemptive-repeat ( prt ), in which case the
                 interrupted job needs to restart from the beginning, or
                 preemptive-resume ( prs ), in which case the job
                 resumes execution from the point of interruption. Using
                 a semi-Markov process (SMP) to model the server
                 behavior, the steady-state server availability is
                 computed and the theory developed in Kulkarni et al.
                 [1987] is used to obtain the Laplace--Stieltjes
                 transform (LST) of the job completion time. In the
                 numerical experiments, we introduce four types of aging
                 behavior of VMM. The effectiveness of VMM rejuvenation
                 on job completion time is discussed in association with
                 the type of interruption it causes and the VMM aging
                 type. With our parameter settings, VMM rejuvenation
                 with prs job interruption improves the performance of
                 job execution regardless of the aging type, with
                 performance degradation is taken into account.",
  acknowledgement = ack-nhfb,
  articleno =    "10",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Araujo:2014:SAE,
  author =       "Jean Araujo and Rubens Matos and Vandi Alves and Paulo
                 Maciel and F. Vieira de Souza and Rivalino {Matias Jr.}
                 and Kishor S. Trivedi",
  title =        "Software aging in the {Eucalyptus} cloud computing
                 infrastructure: Characterization and rejuvenation",
  journal =      j-JETC,
  volume =       "10",
  number =       "1",
  pages =        "11:1--11:??",
  month =        jan,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2539122",
  ISSN =         "1550-4832",
  bibdate =      "Tue Jan 14 19:15:04 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The need for high reliability, availability and
                 performance has significantly increased in modern
                 applications, that handle rapidly growing demands while
                 providing uninterruptible services. Cloud computing
                 systems fundamentally provide access to large pools of
                 data and computational resources. Eucalyptus is a
                 software framework largely used to implement private
                 clouds and hybrid-style Infrastructure as a Service. It
                 implements the Amazon Web Service (AWS) API, allowing
                 interoperability with other AWS-based services. This
                 article investigates the software aging effects in the
                 Eucalyptus framework, considering workloads composed of
                 intensive requests for remote storage attachment and
                 virtual machine instantiations. We found problems that
                 may be harmful to system dependability and performance,
                 specifically regarding to RAM memory and swap space
                 exhaustion, besides highly excessive CPU utilization by
                 the virtual machines. We also present an approach that
                 applies time series analysis to schedule rejuvenation,
                 so as to reduce the downtime by predicting the proper
                 moment to perform the rejuvenation. We experimentally
                 evaluate our approach using an Eucalyptus test bed. The
                 results show that our approach achieves higher
                 availability, when compared to a threshold-triggered
                 rejuvenation method based on continuous monitoring of
                 resources utilization.",
  acknowledgement = ack-nhfb,
  articleno =    "11",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chen:2014:CRP,
  author =       "Jifeng Chen and Shuo Wang and Mohammad Tehranipoor",
  title =        "Critical-reliability path identification and delay
                 analysis",
  journal =      j-JETC,
  volume =       "10",
  number =       "2",
  pages =        "12:1--12:??",
  month =        feb,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2564926",
  ISSN =         "1550-4832",
  bibdate =      "Fri Feb 28 17:06:25 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Circuit reliability analysis at the presilicon stage
                 has become vital for sub-45nm technology designs in
                 particular, due to aging effects, such as Negative Bias
                 Temperature Instability (NBTI) and Hot Carrier
                 Injection (HCI). To avoid potential reliability hazards
                 in the postsilicon stage, current large-scale designs
                 for commercial implementation overpessimistically
                 analyze circuit aging under assumed worst-case workload
                 in order not to violate the corner cases even for low
                 possibilities, thus introducing unnecessary margin in
                 the design timing analysis. The major issue is lack of
                 an effective aging analysis method applicable to large
                 designs with low CPU runtime, which is mainly due to:
                 (1) conventional reliability tools are extremely
                 time-consuming for circuit-level timing analysis and
                 thus are not practical for large designs; (2)
                 mathematical models developed to expedite the process
                 are not accurate due to the high complexity of aging
                 effects. In this article, a comprehensive analysis is
                 presented to highlight the importance of each aging
                 parameter. Then, a novel methodology is developed based
                 on current commercial reliability tools to guarantee
                 its high accuracy on circuit-level aging analysis.
                 Existing proven low-level mathematical models are
                 further enhanced to extensively speed up a higher level
                 analysis by taking advantage of the explicit
                 intermediate conditions stored in a pregenerated lookup
                 table. Our results indicate $ \geq 244 \times $
                 improved computational efficiency, $ \leq 5 \% $
                 relative error, and $ \leq 0.7 \% $ absolute error
                 compared with commercial reliability analysis tools
                 (e.g., HSPICE MOSRA).",
  acknowledgement = ack-nhfb,
  articleno =    "12",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Gladshtein:2014:DBP,
  author =       "Michael Gladshtein",
  title =        "Delay-based processing-in-wire for design of {QCA}
                 serial decimal arithmetic units",
  journal =      j-JETC,
  volume =       "10",
  number =       "2",
  pages =        "13:1--13:??",
  month =        feb,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2564927",
  ISSN =         "1550-4832",
  bibdate =      "Fri Feb 28 17:06:25 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/fparith.bib;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Quantum-dot cellular automata (QCA) technology is now
                 considered to be one of the prospective technologies
                 for a nanocomputer creation. The physical properties of
                 QCA and its expanding range of computer applications
                 make it expedient to use the novel paradigm of
                 nanocomputer architecture: serial decimal
                 storage-transfer-processing. The delay-based encoding
                 of decimal digits allows the use a delay element as a
                 main element of QCA serial arithmetic units. The simple
                 implementation of the delay element by a short length
                 of QCA wire results in reduction of complexity and of
                 the area required for a QCA circuit. The theoretical
                 basics of delay-based processing-in-wire and design
                 examples of QCA serial decimal arithmetic units are
                 presented.",
  acknowledgement = ack-nhfb,
  articleno =    "13",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Lin:2014:RRM,
  author =       "Chia-Chun Lin and Niraj K. Jha",
  title =        "{RMDDS}: {Reed--Muller} decision diagram synthesis of
                 reversible logic circuits",
  journal =      j-JETC,
  volume =       "10",
  number =       "2",
  pages =        "14:1--14:??",
  month =        feb,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2564923",
  ISSN =         "1550-4832",
  bibdate =      "Fri Feb 28 17:06:25 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this article, we propose a flexible and efficient
                 reversible logic synthesizer. It exploits the
                 complementary advantages of two methods: Reed--Muller
                 Reversible Logic Synthesis (RMRLS) and Decision Diagram
                 Synthesis (DDS), and is thus called Reed--Muller
                 Decision Diagram Synthesis (RMDDS). RMRLS does not
                 scale to a large number of qubits (i.e., quantum bits).
                 DDS tools, even though efficient, add a large number of
                 ancillary qubits and typically incur much higher
                 quantum cost than necessary. RMDDS overcomes these
                 obstacles. It is flexible in the sense that users can
                 either optimize the number of qubits or the quantum
                 cost in the circuit implementation. It is also
                 efficient because the circuits can be synthesized
                 within user-defined CPU times. This combination of
                 flexibility and efficiency has been missing from
                 synthesizers presented earlier. When used to synthesize
                 reversible functions, RMDDS reduces the number of
                 qubits by up to 79.2\% (average of 54.6\%) when the
                 synthesis objective is to minimize the number of qubits
                 and the quantum cost by up to 71.5\% (average of
                 35.7\%) when the synthesis objective is to minimize
                 quantum cost, relative to DDS methods. For irreversible
                 functions (which are automatically embedded in
                 reversible functions), the corresponding best (average)
                 reductions in the number of qubits is 42.1\% (22.5\%)
                 when minimizing the number of qubits, and in quantum
                 cost, it is 63.0\% (25.9\%) when minimizing quantum
                 cost.",
  acknowledgement = ack-nhfb,
  articleno =    "14",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Liu:2014:CSN,
  author =       "Weichen Liu and Xuan Wang and Jiang Xu and Wei Zhang
                 and Yaoyao Ye and Xiaowen Wu and Mahdi Nikdast and
                 Zhehui Wang",
  title =        "On-chip sensor networks for soft-error tolerant
                 real-time multiprocessor systems-on-chip",
  journal =      j-JETC,
  volume =       "10",
  number =       "2",
  pages =        "15:1--15:??",
  month =        feb,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2564928",
  ISSN =         "1550-4832",
  bibdate =      "Fri Feb 28 17:06:25 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "As transistor density continues to increase with the
                 advent of nanotechnology, reliability issues raised by
                 the more frequent appearance of soft errors are
                 becoming critical for future embedded multiprocessor
                 systems design. State-of-the-art techniques for soft
                 error protections targeting multiprocessor systems
                 result either high chip cost and area overhead or high
                 performance degradation and energy consumption, and do
                 not fulfill the increasing requirements for high
                 performance and dependability. In this article we
                 present a systematic approach, that is, the Sensor
                 Networks-on-Chip (SENoC), to collaboratively and
                 efficiently manage on-chip applications and overcome
                 reliability threats to Multiprocessor Systems-on-Chip
                 (MPSoC). A hardware-software collaborative approach is
                 proposed to solve soft error problems: a hardware-based
                 on-chip sensor network is built for soft error
                 detection, and a software-based recovery mechanism is
                 applied for soft error correction. A two-step
                 scheduling scheme is presented for reliable application
                 and chip management, combining an off-line static
                 optimization stage for application performance
                 maximization and an online lightweight dynamic
                 adjustment stage to handle runtime variations and
                 exceptions. This strategy introduces only trivial
                 overhead on hardware design and much lower overhead on
                 software control and execution, and hence performance
                 degradation and energy consumption is greatly reduced.
                 We build a cycle-accurate simulator using SystemC, and
                 verify the effectiveness of our technique by comparing
                 performance with related techniques on several
                 real-world applications.",
  acknowledgement = ack-nhfb,
  articleno =    "15",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Kim:2014:ICU,
  author =       "Jaeyoon Kim and Sandip Tiwari",
  title =        "Inexact computing using probabilistic circuits: Ultra
                 low-power digital processing",
  journal =      j-JETC,
  volume =       "10",
  number =       "2",
  pages =        "16:1--16:??",
  month =        feb,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2564925",
  ISSN =         "1550-4832",
  bibdate =      "Fri Feb 28 17:06:25 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Numerous computing applications can tolerate low error
                 rates. In such applications, inexact approaches provide
                 the ability to achieve significantly lower power. This
                 work demonstrates the power-error trade-offs that can
                 be achieved. Using probabilistic modeling in sub-50-nm
                 silicon transistor technology, the relationship between
                 statistical uncertainties and errors are elucidated for
                 different configurations and topologies and the
                 trade-offs quantified. Gate-level implementation of the
                 probabilistic CMOS logic is validated by circuit
                 simulations of a commercial 45-nm SOI CMOS process
                 technology. Using a practical ALU architecture where
                 voltages can be scaled from most significant to least
                 significant bit blocks as an example, the potential
                 benefits of this technique are shown. A calculation
                 error of $10^{-6}$, an error rate quite tolerable for
                 many computational tasks, is shown to be possible with
                 a total power reduction of more than 40\%.",
  acknowledgement = ack-nhfb,
  articleno =    "16",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Pierce:2014:NTN,
  author =       "Luke Pierce and Spyros Tragoudas",
  title =        "Nanopipelined threshold network synthesis",
  journal =      j-JETC,
  volume =       "10",
  number =       "2",
  pages =        "17:1--17:??",
  month =        feb,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2564924",
  ISSN =         "1550-4832",
  bibdate =      "Fri Feb 28 17:06:25 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Threshold logic gates allow for complex multiinput
                 functions to be implemented using a single gate thereby
                 reducing the power and area of a circuit. Clocked
                 threshold gates are nanopipelined to increase network
                 throughput. It is shown that synthesis methods that do
                 not consider the synchronization of the nanopipeline
                 can produce an enormous amount of buffers. The proposed
                 algorithm synthesizes a Boolean network into a
                 nanopipelined threshold logic network by minimizing not
                 only the number of combinational clusters but also the
                 associated buffer insertion overhead.",
  acknowledgement = ack-nhfb,
  articleno =    "17",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Xiang:2014:TDT,
  author =       "Dong Xiang and Kele Shen",
  title =        "A thermal-driven test application scheme for pre-bond
                 and post-bond scan testing of three-dimensional {ICs}",
  journal =      j-JETC,
  volume =       "10",
  number =       "2",
  pages =        "18:1--18:??",
  month =        feb,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2564922",
  ISSN =         "1550-4832",
  bibdate =      "Fri Feb 28 17:06:25 MST 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "The three-dimensional (3-D) technology offers a new
                 solution to the increasing density of integrated
                 circuits (ICs). In this work, we propose novel scan
                 architectures for 3-D IC pre-bond and post-bond testing
                 by considering the interconnection overhead of
                 through-silicon-vias (TSVs). Since hotspots in 3-D ICs
                 often cause performance and reliability issues, we also
                 develop different test ordering schemes for prebond and
                 postbond testing to avoid applying test vectors that
                 could worsen the temperature distribution. Experimental
                 results show that the peak temperature can be lowered
                 by 20\% with the 3-D scan tree architecture. When
                 combined with the test ordering scheme, the 3-D scan
                 tree can further reduce peak temperature by over
                 30\%.",
  acknowledgement = ack-nhfb,
  articleno =    "18",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Kamal:2014:IPV,
  author =       "Mehdi Kamal and Ali Afzali-Kusha and Saeed Safari and
                 Massoud Pedram",
  title =        "Impact of Process Variations on Speedup and Maximum
                 Achievable Frequency of Extensible Processors",
  journal =      j-JETC,
  volume =       "10",
  number =       "3",
  pages =        "19:1--19:??",
  month =        apr,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2567665",
  ISSN =         "1550-4832",
  bibdate =      "Mon May 5 14:50:39 MDT 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "In this article, we investigate the impact of process
                 variations on the speedup and maximum frequency of the
                 extended ISA processor. First, without considering
                 process variations, a custom functional unit (CFU) is
                 designed based on nominal timing parameters, then the
                 timing variations of critical paths of the extensible
                 processor, including the baseline processor and the
                 CFU, are investigated by considering both systematic
                 and random variations. Next, the maximum frequency of
                 the extensible processor and the speed enhancement
                 factor of the extended ISA for different benchmarks are
                 investigated. Results show that timing variation could
                 reduce the speedup of the extensible processor.
                 However, this reduction is highly dependent on the
                 baseline processor and the CFU structures.
                 Additionally, the impact of process variations in the
                 worst-case design approach is studied. Results show
                 that the speedup of the extensible processor is reduced
                 more than in the case when custom instructions (CIs)
                 are selected without considering process variations. To
                 study the impact of each variation type, speedup
                 variations due to random and systematic variations are
                 investigated separately. The study reveals that random
                 variation has a similar effect on the CFU and the
                 baseline processor, while the impact of systematic
                 variation on the baseline processor is greater than the
                 CFU.",
  acknowledgement = ack-nhfb,
  articleno =    "19",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chung:2014:DET,
  author =       "Haera Chung and Christof Teuscher and Partha Pande",
  title =        "Design and Evaluation of Technology-Agnostic
                 Heterogeneous Networks-on-Chip",
  journal =      j-JETC,
  volume =       "10",
  number =       "3",
  pages =        "20:1--20:??",
  month =        apr,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2567666",
  ISSN =         "1550-4832",
  bibdate =      "Mon May 5 14:50:39 MDT 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Traditional metal-wire-based networks-on-chip (NoC)
                 suffer from high latency and power dissipation as the
                 system size scales up in the number of cores. This
                 limitation stems from the inherent multihop
                 communication nature of larger NoCs. It has previously
                 been shown that the performance of NoCs can be
                 significantly improved by introducing long-range, low
                 power, and high-bandwidth single-hop links between
                 distant cores. While previous work has focused on
                 specific NoC architectures and configurations, it
                 remains an open question whether heterogeneous link
                 types are beneficial in a broad range of NoC
                 architectures. In this article, we show that a generic
                 NoC architecture with heterogeneous link types allows
                 for NoCs with higher bandwidth at a lower cost compared
                 to homogeneous networks. We further show that such NoCs
                 scale up significantly better in terms of performance
                 and cost. We demonstrate these broadly-applicable
                 results by using a technology-agnostic complex network
                 approach that targets NoC architectures with various
                 emerging link types.",
  acknowledgement = ack-nhfb,
  articleno =    "20",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Palaniswamy:2014:ITL,
  author =       "Ashok Kumar Palaniswamy and Spyros Tragoudas",
  title =        "Improved Threshold Logic Synthesis Using
                 Implicant-Implicit Algorithms",
  journal =      j-JETC,
  volume =       "10",
  number =       "3",
  pages =        "21:1--21:??",
  month =        apr,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2597175",
  ISSN =         "1550-4832",
  bibdate =      "Mon May 5 14:50:39 MDT 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Existing threshold logic synthesis methods decompose
                 larger input functions into smaller input functions and
                 perform synthesis for them. It is shown that
                 significantly larger input functions can be synthesized
                 by implementing the existing methods in an
                 implicant-implicit manner. Experimental results on the
                 ISCAS 85 benchmarks show that this impacts the
                 synthesis cost, which drops significantly. More
                 specifically, as the size of the functions that can be
                 handled by the synthesis algorithm increases, the
                 number of threshold logic gates required to implement
                 very large input functions decreases. In addition, the
                 total weight decreases and the performance is
                 improved.",
  acknowledgement = ack-nhfb,
  articleno =    "21",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chen:2014:CTS,
  author =       "Fu-Wei Chen and Tingting Hwang",
  title =        "Clock-Tree Synthesis with Methodology of Reuse in
                 {$3$D-IC}",
  journal =      j-JETC,
  volume =       "10",
  number =       "3",
  pages =        "22:1--22:??",
  month =        apr,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2567668",
  ISSN =         "1550-4832",
  bibdate =      "Mon May 5 14:50:39 MDT 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "IP reuse methodology has been used extensively in SoC
                 (system-on-chip) design. In this reuse methodology,
                 while design and implementation costs are saved,
                 manufacturing cost is not. To further reduce the cost,
                 this reuse concept has been proposed at mask and die
                 level in three-dimensional integrated circuits (3D-IC).
                 In order to achieve manufacturing reuse, in this
                 article, we propose a new methodology for designing a
                 global clock tree in 3D-IC. The objective is to extend
                 an existing clock tree in 2D IC to 3D IC, taking into
                 consideration the wirelength, clock skew, and the
                 number of TSVs. Compared with NNG- and 3D-MMM-based
                 methods, our proposed method reduces the wirelength of
                 the new die and the skew of the global 3D clock tree on
                 average, 5.85\% and 2.3\%, and 76.92\% and 48.7\%,
                 respectively. In more than two die design, the average
                 improvements of the wirelength and clock skew of our
                 method as compared with the 3D-MMM-based method are
                 4.23\% and 46.84\%, respectively.",
  acknowledgement = ack-nhfb,
  articleno =    "22",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Liu:2014:CHP,
  author =       "Wulong Liu and Yu Wang and Yuchun Ma and Yuan Xie and
                 Huazhong Yang",
  title =        "On-Chip Hybrid Power Supply System for Wireless Sensor
                 Nodes",
  journal =      j-JETC,
  volume =       "10",
  number =       "3",
  pages =        "23:1--23:??",
  month =        apr,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2492683",
  ISSN =         "1550-4832",
  bibdate =      "Mon May 5 14:50:39 MDT 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "With the miniaturization of electronic devices,
                 small-size but high-capacity power supply systems
                 appear to be more and more important. A hybrid power
                 source, which consists of a fuel cell (FC) and a
                 rechargeable battery, has the advantages of long
                 lifetime and good load-following capabilities. In this
                 article, we propose the schematic of a hybrid power
                 supply system that can be integrated on a chip
                 compatible with present CMOS processes. For the
                 on-chip, fuel-cell-based hybrid power system in
                 wireless sensor node design, we propose a two steps
                 optimization: (1) dynamic power management (DPM), and
                 (2) adaptive fuel cell optimal power point tracking
                 (AOPPT). Simulation results demonstrate that the
                 on-chip FC-Bat hybrid power system can be used for
                 wireless sensor nodes under different usage scenarios.
                 Our proposed DPM method can achieve 12.9\% more energy
                 savings than the method without DPM. Meanwhile,
                 implementing our AOPPT approach can save about 17\%
                 energy compared with the fixed architecture for the
                 fuel cell system. For an on-chip power system with
                 1cm$^2$ area consumption, the wafer-level battery can
                 power a typical sensor node for only about five months,
                 while our on-chip hybrid power system will supply the
                 same sensor node for two years steadily.",
  acknowledgement = ack-nhfb,
  articleno =    "23",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Grissom:2014:IAC,
  author =       "Daniel Grissom and Christopher Curtis and Philip
                 Brisk",
  title =        "Interpreting Assays with Control Flow on Digital
                 Microfluidic Biochips",
  journal =      j-JETC,
  volume =       "10",
  number =       "3",
  pages =        "24:1--24:??",
  month =        apr,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2567669",
  ISSN =         "1550-4832",
  bibdate =      "Mon May 5 14:50:39 MDT 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "BioCoder is a C++ library developed at Microsoft
                 Research, India, for the unambiguous specification of
                 biochemical assays. This article describes language
                 extensions to BioCoder along with a compiler and
                 runtime system that translate and execute assays
                 specified using BioCoder on a software simulator. The
                 simulator mimics the behavior of laboratories-on-a-chip
                 (LoCs) based on a droplet actuation technology called
                 electrowetting on dielectric (EWoD). To date, prior
                 compilers targeting similar EWoD devices are limited to
                 assays specified as directed acyclic graphs (DAGs) and
                 cannot handle arbitrary control flow or feedback from
                 the LoC. The framework presented herein addresses these
                 challenges through dynamic interpretation, thereby
                 enlarging the space of assays that can be compiled onto
                 EWoD devices.",
  acknowledgement = ack-nhfb,
  articleno =    "24",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Yuan:2014:FEA,
  author =       "Bo Yuan and Bin Li",
  title =        "A Fast Extraction Algorithm for Defect-Free
                 Subcrossbar in Nanoelectronic Crossbar",
  journal =      j-JETC,
  volume =       "10",
  number =       "3",
  pages =        "25:1--25:??",
  month =        apr,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2517137",
  ISSN =         "1550-4832",
  bibdate =      "Mon May 5 14:50:39 MDT 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Due to the super scale, high defect density, and
                 per-chip designing paradigm of emerging
                 nanoelectronics, the runtime of the algorithms for
                 defect-tolerant design is of vital importance from the
                 perspective of practicability. In this article, an
                 efficient and effective heuristic defect-free
                 subcrossbar extraction algorithm is proposed which
                 improves performance by mixing the heuristics from two
                 state-of-the-art algorithms and then is speeded up
                 significantly by considerably reducing the number of
                 major loops. Compared with the current most effective
                 algorithm that improves the solution quality (i.e.,
                 size of the defect-free subcrossbar obtained) at the
                 cost of high time complexity O ( n$^3$ ), the time
                 complexity of the proposed heuristic algorithm is
                 proved to be O ( n$^2$ ). Using a large set of
                 instances of various scales and defect densities, the
                 simulation results show that the proposed algorithm can
                 offer similar high-quality solutions as the current
                 most effective algorithm while consuming much shorter
                 runtimes (reduced to about 1/3 to 1/5) than the current
                 most effective algorithm.",
  acknowledgement = ack-nhfb,
  articleno =    "25",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}

@Article{Chaudhuri:2014:VDS,
  author =       "Sourindra M. Chaudhuri and Niraj K. Jha",
  title =        "{$3$D} vs. {$2$D} Device Simulation of {FinFET} Logic
                 Gates under {PVT} Variations",
  journal =      j-JETC,
  volume =       "10",
  number =       "3",
  pages =        "26:1--26:??",
  month =        apr,
  year =         "2014",
  CODEN =        "????",
  DOI =          "http://dx.doi.org/10.1145/2567670",
  ISSN =         "1550-4832",
  bibdate =      "Mon May 5 14:50:39 MDT 2014",
  bibsource =    "http://www.acm.org/pubs/contents/journals/jetc/;
                 http://www.math.utah.edu/pub/tex/bib/jetc.bib",
  abstract =     "Recently, multigate transistors have been gaining
                 attention as an alternative to conventional MOSFETs.
                 Superior gate control over the channel, smaller
                 subthreshold leakage, and reduced susceptibility to
                 process variations are some of the key features that
                 give multigate structures a competitive edge over
                 MOSFETs. Among various multigate structures,
                 silicon-on-insulator (SOI) FinFETs are promising, owing
                 to their ease of fabrication. However, characterization
                 of SOI FinFET devices/gates needs immediate attention
                 in order for them to gain greater popularity in this
                 decade. Ideally, 3D device simulation should be done
                 for accurate circuit analysis. However, this is
                 impractical due to the huge CPU time required. As a
                 possible alternative, simulating a 2D crosssection of
                 the device yields 10$ \times $ to 100$ \times $
                 reduction in CPU time. However, this introduces
                 significant error in the range of 7\% to 20\% when
                 evaluating the on/off current ( I$_{ON}$ /I$_{OFF}$ )
                 for a single device and leakage current or propagation
                 delay ( I$_{LEAK}$ /t$_D$ ) for logic gates. In this
                 work, we first present a methodology to obtain
                 optimized 3D device simulation models for SOI FinFETs.
                 Based on these 3D models, we develop adjusted 2D models
                 to capture 3D simulation accuracy with 2D simulation
                 efficiency. We report results for the 22nm SOI FinFET
                 technology node. We adjust gate underlap ( L$_{UN}$ )
                 in the 2D cross section of the n/pFinFET devices in
                 order to mimic 3D device behavior. When the adjusted 2D
                 models are employed in mixed-mode simulation of FinFET
                 logic gates, the error in the evaluation of I$_{LEAK}$
                 /t$_D$ is very small. To the best of our knowledge,
                 this is the first such attempt. We show that 2D device
                 models remain valid even under process, voltage, and
                 temperature (PVT) variations. We target process
                 variations in gate length ( L$_G$ ), fin thickness (
                 T$_{SI}$ ), gate oxide thickness ( T$_{OX}$ ), and gate
                 workfunction ( \Phi $_G$ ), which are the parameters
                 that have been shown to have the most impact on leakage
                 and delay.",
  acknowledgement = ack-nhfb,
  articleno =    "26",
  fjournal =     "ACM Journal on Emerging Technologies in Computing
                 Systems (JETC)",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J967",
}