#!Paragon-XPS150
##PROBLEM SIZE T42L16 (SMALL),
##OPTIMISATION LEVEL 0,
##Dr Patrick H. Worley,
##Oak Ridge National Laboratory,
#
#Performance calculated using time (/s) / 14339 (MFlop) for 216 timesteps
#
#System Description
#------------------
#
#11/17/95
#  XPS150
#  if77/Paragon Paragon Version R5.2
#  if77 flags: -O4 -Mnodepchk -Knoieee
#  Paragon Software Release R1.3.3
#  mpich 1.0.11 (arch=paragon device=nx)
#
#Timing Tables
#-------------
#make MACH=paragon COMM=mpich WORKSPACE=6700000
#
#         optimization level 0   
#T42L16 
#proc	perf MFLOP/s
1 	7.3349	#1954.9s
2 	12.4893	#1148.1s
4 	24.8196	#577.73s
8 	48.8103	#293.77s
16 	98.2258	#145.98s
32  	194.1376	#73.86s
64  	363.6571	#39.43s
128  	638.9929	#22.44s
256  	917.9898	#15.62s
#
#Notes:
#1) Mapped logical processor mesh to physcial processor mesh for all
#   processor numbers up to 512 (see -sz specifications). For 1024,
#   can map 32x32 logical mesh directly onto 16x64 physical processor
#   mesh. Results are provided both for the default mapping and for a
#   specific nearest neighbor "preserving" map for level 0 optimization.
#   Level 1 optimization for 1024 processors also uses the improved
#   mapping.
#2) Missing optimization level 1 values denote problem sizes in which
#   options better than the default have not yet been identified.