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To: pbwg-lowlevel@cs.utk.edu
Subject: Draft Report Chapter-2

                   FIRST DRAFT LOW-LEVEL CHAPTER
                   -----------------------------

I have put together below my thoughts on the contents of the low-level
benchmarks, which are mostly what we have at Southampton and in my
own work. This is for comment and to merge with contributions from
other subcommittee members (none in yet), and finally for presentation to 
24 May 1993 meeting of PBWG.
     I believe we need basic multi-processor benchmarks to measure
various global operations in addition to SYNCH1 (e.g. global sum and 
multiply reduction, global 'or' and 'and', etc). Perhaps other members have 
these or would like to write benchmarks and suggest appropriate metrics 
to use.
     I heard some talk about the alpha and beta parameters at the last
meeting. Can someone tell me what they measure and send me the appropriate
reference. Thank you,
                   Yours sincerely
                         Roger Hockney 
            (leader low-level benchmark subcommittee)
There follows latex version of draft of low-level chapter
------------------------  cut here  -----------------------------------------
%file: lowlev1.tex
\chapter{Low-Level Benchmarks}
\footnote{assembled by Roger Hockney for low-level subcommittee}

\section{Single-Processor Benchmarks}

\subsection{Timer resolution: TICK1}

TICK1 measures the interval between ticks of the clock being used
in the benchmark measurements. That is to say the resolution of
the clock. A succession of calls to the timer routine are inserted
in a loop and executed many times. The differences between successive
values given by the timer are then examined.  If the changes in the
clock value (or ticks) occur less frequently than the time taken to 
enter and leave the timer routine, then most of these differences
will be zero. When a tick takes place, however, a difference equal 
to the tick value will be recorded, surrounded by many zero differences. 
This is the case with clocks of poor resolution, for example most UNIX 
clocks that tick typically every 10 ms. Such poor UNIX clocks can still
be used for low-level benchmark measurements if the benchmark is
repeated, say, 10,000 times, and the timer calls are made outside this 
repeat loop.  

With some computers, such as the
CRAY series, the clock ticks every cycle of the computer, that is to say
every 6ns on the Y-MP. The resolution of the CRAY clock is therefore
approximately one million times better than a UNIX clock, and that is
quite a difference! If TICK1 is used on such a computer the difference
between successive values of the timer is a very accurate measure of
how long it takes to execute the instructions of the timer routine, and
therefore is never zero. TICK1 takes the minimum of all such differences,
and all it is possible to say is that the clock tick is less than or
equal to this value. Typically this minimum will be several hundreds
of clock ticks. With a clock ticking every computer cycle, we can make
low-level benchmark measurements without a repeat loop. Such measurements
can even be made on a busy timeshared system (where many users are
contending for memory access) by taking the minumum time recorded from
a sample of, say, 10,000 single execution measurements. In this case,
the minimum can usually be said to apply to a case when there was no
memory access delay caused by other users.

TICK1 exists and forms part of the Genesis benchmarks v2.0 and v2.1.1
 ~\cite{Hey91}.

\subsection{Timer value: TICK2}

TICK2 confirms that correctness of the time values returned by the
computer clock, by comparing its measurement of a given time interval
with that of an external wall-clock (actually the benchmarker's 
wristwatch). Parallel benchmark performance can only be measured
using the elapsed wall-clock time, as the objective of
parallel execution is to reduce this time. Measurements made with a
CPU-timer (which only records time when its job is executing in the CPU) 
are clearly incorrect, because the clock does not record waiting time 
when the job is out of the CPU. TICK2 will immediately detect the 
incorrect use of a CPU-time-for-this-job-only clock. An example
of a timer that claims to measure elapsed time but is actually a
CPU-timer, is the returned value of the popular Sun UNIX timer ETIME. 
TICK2 also checks that the correct multiplier is being used in the 
computer system software to convert clock ticks to true seconds.  

TICK2 exists and will form part of the next release of the Genesis 
benchmarks v2.2 ~\cite{Hey91}.


\subsection{Most Reported Benchmark: LINPACKD (n=100)}

This well-known standard benchmark is a Fortran program
for the solution of (100x100) dense set of linear equations by
Gaussian elimination. It is distributed by Dr J. J. Dongarra of
the University of Tennessee. The results are quoted in Mflop/s
and are regularly published and available by electronic mail.
The main value of this benchmark is that results are known for 
more computers than any other benchmark. Most of the compute time 
is contained in vectorisable DO-loops such as the DAXPY (scalar 
times vector plus vector) and inner product. Therefore one expects 
vector computers to perform well on this benchmark. The weakness 
of the benchmark is that it tests only a small number of vector 
operations, but it does include the effect of memory access and
it is solving a complete (although small) real problem. 

\subsection{Performance Range: The Livermore Loops}

These are a set of 24 Fortran DO-loops (or kernels) 
extracted from operational codes used at the Lawrence Livermore 
National Laboratory \cite{Ma88}. They have been used since the early 
seventies to assess the arithmetic performance of computers and their 
compilers. They are a mixture of vectorisable and non-vectorisable
loops and test rather fully the computational capabilities of the
hardware, and the skill of the software in compiling efficient code,
and in vectorisation. The main value of the benchmark is the range
of performance that it demonstrates, and in this respect it 
complements the limited range of loops tested in the LINPACK benchmark. 
The benchmark provides the individual performance of each loop,
together with various averages (arithmetic, geometric, harmonic)
and the quartiles of the distribution. However, it is difficult to
give a clear meaning to these averages, and the value of the benchmark
is more in the distribution itself.  In particular, the maximum and
minimum give the range of likely performance in full applications.
The ratio of maximum to minimum performance has been called the
{\em instability} or the {\em speciality} ~\cite{Hoc91}, and is a measure 
of how difficult it is to obtain good performance from the computer,
and therefore how specialised it is. The minimum or worst performance
obtained on these loops is of special value, because there is much
truth in the saying that "the best computer to choose is that with 
the best worst-performance".


\subsection{Basic Arithmetic Operations: RINF1}

This benchmark takes a set of common Fortran DO-loops and analyses
their time of execution in terms of the two parameters \rnhalf
~\cite{Hoc77,HoJe81,Hoc82,Hoc83,Hoc87,HoJe88}. \rinf is the 
asymptotic performance rate in Mflop/s which 
is approached as the loop (or vector) length ,$n$, becomes longer. \nhalf 
(the half-performance length) expresses how rapidly, in terms
increasing vector length, the actual performance, $r$, approaches \rinf. 
It is defined as the vector length required to achieve a performance 
of one half of \rinf. This means that the time, $t$, for a DO-loop
corresponding to $v$ vector operations (i.e. with $v$ floating-point 
operations per element per iteration) is approximated by:
\begin{equation}
                  t = v * ( n + \nhalf ) / \rinf          \label{Eqn1}
\end{equation}      
         Then the performance rate is given by
\begin{equation}
        r =  \frac{v*n}{t} = \frac{\rinf}{(1+\nhalf /n)}   \label{Eqn2}
\end{equation}                                        
We can see from Eqn.(\ref{Eqn1}) that \nhalf is a way of measuring the
importance of vector startup overhead (=\nhalf/\rinf) in terms
of quantities known to the programmer (loop or vector length).
In the benchmark program, the two parameters are determined by a
least-squares fit of the data to the straight line defined by 
Eqn.(\ref{Eqn1}). A useful guide to the significance of \nhalf is to note
from Eqn.(\ref{Eqn2}) that 80 percent of the asymptotic performance is
achieved for vectors of length $4*\nhalf$. Generally speaking, \nhalf
values of upto about 50 are tolerable, whereas the performance
of computers with larger values of \nhalf is severely constrained
by the need to keep vector lengths significantly longer than \nhalf.
This requirement makes the computers difficult to program efficiently,
and often leads to disappointing performance, compared to the
asymptotic rate advertised by the manufacturer.  

RINF1 exists as part of the Hockney and Genesis benchmarks v2.0 and v2.1.1
~\cite{Hey91}. 
An independently written version forms module MOD1AC of the EuroBen
benchmarks ~\cite{StRi93}.


\subsection{Memory-Bottleneck Benchmarks: POLY1 and POLY2}

Even if the vector lengths are long enough to overcome the vector 
startup overhead, the peak rate of the arithmetic pipelines may not
be realised because of the delays associated with obtaining data
from the cache or main memory of the computer. The POLY1 benchmark attempts 
to quantify this dependence of computer performance on memory access
bottlenecks. The computational intensity, $f$, of a DO-loop is defined 
as the number of floating-point operations (flop) performed per memory 
reference (mref) to an element of a vector variable ~\cite{HoJe88}. 
The asymptotic performance, \rinf, of a computer is observed to increase 
as the computational intensity increases, because as this
becomes larger, the effects of memory access delays become negligible
compared to the time spent on arithmetic. This effect is characterised
by the two parameters (\rhat,\fhalf), where \rhat~ is the peak hardware
performance of the arithmetic pipeline, and \fhalf is the computational
intensity required to achieve half this rate. That is to say the
asymptotic performance is given by:
\begin{equation}
              \rinf = \frac{\rhat}{(1+\fhalf/f)}          \label{Eqn3}
\end{equation}                                        
If memory access and arithmetic are not overlapped, then \fhalf can
be shown to be the ratio of arithmetic speed (in Mflop/s) to memory
access speed (in Mword/s). The parameter \fhalf, like \nhalf, measures 
an unwanted overhead
and should be as small as possible. In order to vary $f$ and allow
the peak performance to be approached, we choose a kernel loop that
can be computed with maximum efficiency on any hardware. This is the
evaluation of a polynomial by Horner's rule, in which case the
computational intensity is the order of the polynomial, and both the
multiply and add pipelines are used. To measure \fhalf, the order of 
the polynomial is increased from one to ten, and the measured 
performance for long vectors is fitted to Eqn.(\ref{Eqn3}).

The POLY1 benchmark repeats the polynomial evaluation for each order
typically 1000 times for vector lengths upto 10,000, which would 
normally fit into the cache of a cache-based processor. Except for 
the first evaluation the data will therefore be found in the cache. 
POLY1 is therefore an {\em in-cache} test of the memory bottleneck 
between the arithmetic registers of the processor and its cache. 

POLY2, on the other hand, flushes the cache prior to each different
order and then performs only one polynomial evaluation,
for vector lengths from 10,000 upto 100,000, which would normally
exceed the cache size. Data will have to be brought from off-chip
memory, and POLY2 is an {\em out-of-cache} test of the memory
bottleneck between off-chip memory and the arithmetic registers.

The POLY1 benchmark exists as MOD1G of the EuroBen benchmarks 
~cite{StRi93}. POLY2 exists as part of the Hockney benchmarks.


\subsection{Arithmetic Benchmark Results}

As an indication of the type of results given by the proposed low-level
arithmetic benchmarks, Table-\ref{Table1} gives measurements made on a 
number of workstations, and microprocessor chips that are used as 
processing nodes in multiprocessor MIMD computers. 


\begin{table}
\centering
{\small
\parbox{5in}{\caption{\label{Table1}
Performance of some common numerical benchmarks on some common workstations 
and microprocessor chips used in MIMD computers. Measurements were made with 
the highest level of optimisation that ran, and are in Mflop/s for 64-bit 
precision, except where stated in parentheses. The units of \nhalf are vector 
length, and \fhalf are flop/mref (floating-point operations per memory 
reference). Results are for the best generally available compiler on the 
date shown. Those for the i860 are for the first Greenhills compiler which 
is known not to use many important i860 hardware features. 
Later more advanced compilers should give significantly better results.  
}}
\begin{tabular}{lccccccc}
\hline
               &Sun   &Solbourne&Stardent&Inmos&Intel&IBM RS/  &DEC   \\
 Benchmark     &Sparc1&System 5 &TS2025 &T800  &i860 &6000-530 &$\alpha$\\
               &      &         &       &20MHz &40MHz& 25MHz   &133MHz \\
\hline
      d/m/y &18/1/90&25/1/90 &8/8/89 &15/4/89&6/8/90&14/6/90&13/1/93  \\  
%           m/y & 1/90 &  1/90   &  8/89 &  4/89 & 8/90 & 6/90 & 1/93  \\  
\hline
   Linpackd    & 1.27 &  2.79   & 4.32  & 0.33  & 3.89 & 9.54 & 20.7  \\
     n=100 \\
\hline
   Livermore   & 2.36 &  4.64   &       & 0.72  & 8.76 & 31.8 & 46.6  \\
     Maximum \\
\hline
   Livermore   & 0.45 &  0.89   & 0.45  & 0.10  & 0.47 & 1.34 & 4.47  \\
     Minimum \\
\hline
   RINF1(32') \\
   \rinf      & 1.29 &  2.50   &19.29  &  0.34 & 4.62  & 5.13 & 33.8  \\
  (\nhalf)    &(0.30)& (1.00)  &(1.03) &   (0) &(3.61) &      &(12.2) \\
\hline
   POLY1 \\
   \rhat      & 2.50 &  5.18   &42.31  &        &10.59   &25.85 & 88.9\\
  (\fhalf)    &(0.77)& (0.60)  &(0.51) &        &(1.12)  &(0.34)& (0.71)\\
\hline
\hline
\end{tabular}
}
\end{table}

Table-\ref{Table1} shows that the DEC $\alpha$ chip outperforms
all other workstations and chips on all benchmarks by a significant 
margin, as befits the start of a new generation of chips. However, one 
cannot help being impressed by the figures. The remaining workstations 
and chips are compared with each other below.

Table-\ref{Table1} shows that the IBM RS/6000 chip set performs 
best on the LINPACKD100 benchmark, followed by the Stardent ST2025 
which has a vector architecture. 
The i860 performs significantly worse than the IBM 6000. However
the benchmark performance of both machines is expected to improve 
as their compilers develop.

Table-\ref{Table1} gives the maximum and minimum 
performance observed in the 24 Livermore loops. 
The minimum performance can be taken as giving the 
worst scalar arithmetic performance that is likely to be found, 
and the maximum gives the best performance that is likely to be 
seen on highly vectorisable loops. The computer with the best 
worst-performance, which is a very good metric to examine, is 
the IBM RS/6000 followed by the Solbourne. The best maximum 
performance is seen in the RS/6000 followed by the i860.

The RINF1 benchmark gives values of the \rnhalf parameters for the kernel 
A=B*C (vector = vector $\times$ vector), and shows the Stardent ST2025 
performing best with the
highest \rinf and lowest \nhalf, followed by the IBM RS/6000. 

The POLY1 benchmark shows 
the Stardent ST2025 with the highest peak performance, followed 
by the IBM RS/6000 and then the i860. Of these three, the value for 
the IBM is best, and the Stardent quite low, but the value greater 
than one for the i860 shows that there is a severe memory bottleneck 
problem with this chip that will prevent it from getting close to its
peak advertised performance on many problems.


\section{Multi-Processor Benchmarks}


\subsection{Communication Benchmarks: COMMS1 and COMMS2}

The purpose of the COMMS1, or {\em Pingpong}, benchmark \cite{Hoc88,Hoc91} 
is to measure the basic communication properties of a message-passing MIMD 
computer. A message of variable length, $n$, is sent from a master node to 
a slave node. The slave node receives the message into a Fortran data array, 
and immediately returns it to the master.  
Half the time for this `pingpong' exchange is recorded as the
time, $t$, to send a message of length, $n$.  
In the COMMS2 benchmark there is a message exchange in which two nodes 
simultaneously send messages to each other and return them. In this case
advantage can be taken of bidirectional links, and a greater bandwidth
obtained than is possible with COMMS1. 
In both benchmarks, the time as a function of
message length is fitted by least squares using the parameters
\rnhalf \cite{Hoc82,HoJe88} to the following linear timing model:
\begin{equation}
                     t = (n + \nhalf)/\rinf            \label{Eqn(4.1)}
\end{equation}
when the average communication rate is given by
\begin{equation}
    r = \frac {\rinf}{1+\nhalf/n} = \rinf \pipe (n/\nhalf) \label{Eqn(4.2)}
\end{equation}
\begin{equation}
\where \spten   \pipe (x) = \frac {1}{1 + 1/x}
\end{equation}
and the startup time is
\begin{equation}
                     t_0 = \nhalf/\rinf                \label{Eqn(4.3)}
\end{equation}
In the above equations, \rinf is the {\em asymptotic bandwidth} of 
communication
which is approached as the message length tends to infinity (hence the
subscript), and \nhalf is the message length required to achieve half
this asymptotic rate. Hence \nhalf is called the {\em half-performance
message length}. 

The importance of the parameter \nhalf is that it provides a yardstick with
which to measure message-length, and thereby enables one to distinquish 
the two regimes of short and long messages. 
For long messages $(n > \nhalf)$, the denominator in equation \ref{Eqn(4.2)}
is approximately unity and the average communication rate is approximately
constant at its asymptotic rate, \rinf 
\begin{equation}
                   r \approx \rinf                    \label{Eqn(4.3.5)}
\end{equation} 
For short messages $(n < \nhalf)$, the communication rate is best 
expressed in the algebraically equivalent form
\begin{equation}
                 r = \frac {\pi_0 n} {(1+ n/ \nhalf)}   \label{Eqn(4.4)}
\end{equation}
\begin{equation}
\where \spten     \pi_0 = t_0 ^{-1} = \rinf/\nhalf      \label{Eqn(4.5)}
\end{equation} 
For short messages, the denominator in equation \ref{Eqn(4.4)} will be 
approximately unity, so that
\begin{equation}
                 r \approx \pi_0 n = n / t_0            \label{Eqn(4.6)}
\end{equation}
In sharp contrast to the approximately constant rate in the long-message 
limit, the communication rate in the short message limit is seen to be 
approximately proportional to the message length. 
The constant of proportionality, $\pi_0$, is known
as the {\em specific performance}, and can be expressed conveniently
in units of kilobyte per second per byte (kB/s)/B or k/s. 

Thus, in general, we may say that \rinf characterises the long-message 
performance and $\pi_0$ the short-message performance. The COMMS1 benchmark 
computes all four of the above parameters, 
$(\rinf, \nhalf, t_0, \rmand \pi_0)$,
because each emphasises a different aspect of performance. However only 
two of them are independent. In the case that there are different modes
of transmission for messages shorter or longer than a certain length, the
benchmark can read in this breakpoint and perform a separate least-squares 
fit for the two regions. An example is the Intel iPSC/860 which has a different
message protocol for messages shorter than and longer than 100 byte. 

Because of the finite (and often large) value 
of $t_0$, the above is a {\em two-parameter} description of communication 
performance. It is therefore incorrect, and sometimes positively misleading,
to quote only one of the parameters (e.g. just \rinf, as is often done) to
describe the performance. The most useful pairs of parameters are \rnhalf
$(\pi_0,\nhalf)$ and $(t_0,\rinf)$, depending on whether one is concerned
with long vectors, short vectors or a direct comparison with hardware times. 
Note also that, although \nhalf is defined
as the  message length required to obtain half the asymptotic rate \rinf,
the two parameters \rnhalf are sufficient to calculate the average rate for
any message length via equation \ref{Eqn(4.2)}, or equivalently using 
$\pi_0$ instead of \rinf via \ref{Eqn(4.4)}.

The COMMS1 and COMMS2 benchmarks exist as part if the Genesis benchmarks
v2.0 and 2.2.1 ~\cite{Hey91}.

\subsection{Example Results for the COMMS1 benchmark}

We report below results for the COMMS1 benchmark on the \Suprenum,
and Intel iPSC/860 ~\cite{Hoc91} and Touchstone Delta ~\cite{HoCa92} 
computers. 

Table-\ref{Table4.1} gives the values obtained for the communication 
parameters, in the version of the benchmark using the native \Suprenum
extensions to the Fortran90 language. These include a SEND and RECEIVE
language statement with a syntax similar to that of the Fortran READ
and WRITE statement.
The asymptotic stream rate, or bandwidth, (\rinf) shows considerable
variation on the Suprenum, depending on how the data to be transferred
is specified in the I/O list of the SEND statement.  A variable length
array in Fortran90 syntax in single precision achieves 0.67 MB/s,
whereas the same statement specified in double precision achieves 4.8
MB/s.   This double-precision rate is about twice that observed
on the iPSC/860 with their CSEND Fortran subroutine, which sends an array 
whose length is specified in bytes. The principal difference between the 
two computers is the magnitude of the startup time, $t_0$, which is 
$73\mu s$ on the iPSC/860 compared with about 3ms on the Suprenum.  Since 
the startup time, via $\pi_0$, determines the transfer rate for short 
messages (say $<100$B), we see that the Suprenum is 45 times slower than 
the iPSC/860 for short messages. On the other hand the Suprenum has almost 
twice the stream rate for long messages (as seen by the value of \rinf), 
provided the most favourable format (i.e. double precision or 64-bit)
is used in the I/O list.  One may compute from these numbers that the
iPSC/860 is faster at transferring messages for all message lengths
less than 16,481 Byte. The longer startup time on Suprenum results in 
larger values of \nhalf, showing that longer messages are needed to 
achieve any given fraction of the asymptotic rate.

The results for the Touchstone Delta show that this computer has the
fastest short and long message performance, judged respectively by the
values of $\pi_0$ and \rinf. However the improvement of short message
performance over the iPSC/860 is only marginal, and the long message 
performance is only about one quarter of the advertised bandwidth of 
25MB/s. However harware and software improvements made since the 
measurements were made should have improved the results.

\begin{table}
\centering
{\small
\parbox{3.5in}{
\caption{\label{Table4.1}
          Values of (\rinf,\nhalf) for the communication of messages
          between two nodes of the same cluster on the Suprenum and 
          neighbouring nodes on the Intel iPSC/860 and Touchstone
          Delta computers. The Delta measurements were made on 17 Jan.
          1992, and should have been improved by subsequent hardware
          and software changes.}}
\begin{tabular}{llcccc}
\hline
Specification   & Range      & \rinf   & \nhalf   & $t_0$  & $\pi_0$   \\
                & B*         & MB/s    & B        & ms     & k/s       \\
\hline
   SUPRENUM                                                            \\
sp SEND A(1:N)  &            & 0.67    &  2041    & 3.05   & 0.328     \\
dp SEND A(1:N)  &            & 4.82    & 12740    & 2.64   & 0.378     \\
\hline
   INTEL iPSC/860                                                      \\
CSEND (,A,N,,)  & $N<100$    & 2.36    & 179      & 0.074  & 13.5      \\
                & $N>100$    & 2.80    & 560      & 0.200  &  5.0      \\
\hline
   INTEL Delta                                                         \\
CSEND (,A,N,,)  & $N<512$    & 3.48    & 213      & 0.061  & 16.3      \\
                & $N>512$    & 6.76    & 892      & 0.132  & 7.57      \\
\hline
* B - byte

\end{tabular}
}
\end{table}

% ----------------------------------------------------------------------------



\subsection{Total Saturation Bandwidth: COMMS3}

To complement the above communication benchmarks, there is a need for
a benchmark to measure the total saturation bandwidth of the complete
communication system, and to see how this scales with the number
of processors. A natural generalisation of the COMMS2 benchmark
could be made as follows, and be called the COMMS3 benchmark:
Each processor of a $p$-processor system send a message of length $n$
to the other $(p-1)$ processors. Each processor then waits to receive
the $(p-1)$ messages directed at it. The timing of this generalised
'pingping' ends when all messages have been sucessfully received by all
processors; although the process will be repeated many times to obtain
an accurate measurement, and the overall time will be divided by the
number of repeats. The time for the generalised pingping is the time to
send $p(p-1)$ messages of length $n$ and can be analysed in the same way
as COMMS1 and COMMS2 into values of \rnhalf. The value obtained for \rinf
is the required total saturation bandwidth, and we are interested in how
this scales up as the number of processors $p$ increases and with it the
number of available links in the system.

This benchmark does not exist, but Roger Hockney will develop a trial
version for the Intel iPSC, followed by PARMACS and PVM. Perhaps suitable 
and better benchmarks exist elsewhere. Please send in your suggestions.


\subsection{Communication Bottleneck: POLY3}

POLY3 assesses the severity of the communication bottleneck.
It is the same as the POLY1 benchmark except that the data for the
polynomial evaluation is stored on a neighbouring processor. The value of
\fhalf obtained therefore measures the ratio of arithmetic to communication
performance. Equation ~\ref{Eqn3} shows that the computational intensity 
of the calculation must be significantly greater than \fhalf (say 4 times
greater) if communication is not to be a bottleneck. In this case
the computational intensity is the ratio of arithmetic performed on a
processor to words tranferred to/from it over communication links.
In the common case that the amount of arithmetic is proportional to
the volume of a region, and the data communicated is proportional to
the surface of the region, the computational intensity is increased as
the size of the region (or granularity of the decomposition) is increased. 
Then the \fhalf obtained from this benchmark is directly related 
to the granularity that is required to make communication time unimportant.

The POLY3 benchmark does not exist, although native versions have been
used on transputer systems ~\cite{Hoc91}. A trial benchmark will be 
prepared for Intel iPSC computers by Roger Hockney, followed by PARMACS 
and PVM versions.


\subsection{Synchronisation Benchmarks: SYNCH1}

SYNCH1 measures the time to execute a barrier synchronisation statement
as a function of the number of processes taking part in the barrier.
The practicability of massively parallel computation with thousands
or tens of thousands of processors depends on this barrier time not
increasing too fast with the number of processors. The results are quoted
both as a barrier time, and as the number of barrier statements
executed per second (barr/s).

The SYNCH1 benchmark exists as part of Genesis v2.0 and v2.1.1 ~\cite{Hey91}.


\section{Summary of Benchmark Status}

The following Table-\ref{Table3} summarises the current state of the 
proposed low-level benchmarks, and the properties they are intended
to measure.

\begin{table}
\centering
{\small
\parbox{5in}{
\caption{\label{Table3}
          Status of proposed Low-Level benchmarks. Note we abbreviate
          performance (perf.), arithmetic (arith.), communication (comms.),
          operations (ops.).}}
\begin{tabular}{llcccc}
\hline
Benchmark       & Measures             & Parameters & Exists &  Author     \\
                &                      &            &        &             \\
\hline
SINGLE-PROCESSOR                                                           \\
   TICK1        & Timer resolution     & tick interval & Genesis & Hockney \\
   TICK2        & Timer value          & wall-clock check& Genesis & Hockney \\
   LINPACKD100  & typical arith. perf. & job Mflop/s  & Linpack & Dongarra  \\
   LIVERMORE    & Arith. perf. range   & loop Mflop/s & Livermore & McMahon \\
   RINF1        & Basic Arith. ops.    & \rnhalf    & Genesis & Hockney \\
   POLY1        & Cache-bottleneck     & \rfhalf    & EuroBen & Hockney \\
   POLY2        & Memory-bottleneck    & \rfhalf    & Hockney & Hockney \\
\hline
MULTI-PROCESSOR                                                         \\
   COMMS1       & Basic Message perf.  & \rnhalf    & Genesis & Hockney \\
   COMMS2       & Message exch. perf.  & \rnhalf    & Genesis & Hockney \\
   COMMS3       & Saturation Bandwidth & \rnhalf    & No      & Hockney \\
   POLY3        & Comms. Bottleneck    & \rfhalf    & No      & Hockney \\
\hline

\end{tabular}
}
\end{table}

% ----------------------------------------------------------------------------

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From owner-parkbench-comm@CS.UTK.EDU Fri May  2 15:53:02 1997
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Dear Colleague,

Here is the revised agenda.
Please send me ASAP a short email if you come
so that we can arrange for a meeting room.

-------------------
The ParkBench (Parallel Benchmark Working Group)
will meet in Knoxville, Tennessee on
May 9th, 1997.

The meeting site will be the Knoxville Downtown Hilton Hotel.
We have made arrangements with the Hilton Hotel in Knoxville.

  Hilton Hotel
  501 W. Church Street
  Knoxville, TN
  Phone:  423-523-2300

When making arrangements tell the hotel you are associated with
the 'ParkBench'. The rate about $79.00/night.
You can download a postscript map of the area by looking at
http://www.netlib.org/utk/people/JackDongarra.html.

----------------
The tentative agenda for the meeting is:

  1. Minutes of last meeting (MBe)

     Changes to Current release:
  2. Low Level (ES, VG, RS)
     comms1, comms2, comms3, poly2
  3. Linear Algebra (ES)
  4. Compact Applications - NPBs (SS, ES)

     New benchmarks:
  5. HPF Low Level benchmarks (MBa)
  6. Java Low-Level Benchmarks (VG)
  7. New I/O benchmark benchmarks (MBa)
  8. New performance database design and new benchmark output format
     Update of GBIS with new Web front-end (MBa,TH)

     Report from other benchmark activities
  9. ASCI Benchmark Codes (AH)
 10. SPEC-HPG (RE, JD)

     ParkBench:
 11. ParkBench Bibliography
 12. ParkBench Report 2

     Other Activities:
 13. Discussion of the ParkBench Workshop 11/12 September, UK (TH, MBa)
 14. PEMCS - "Electronic Benchmarking Journal" - status report - (TH, MBa)
 15. Status of Funding proposals (JD, TH)

 15. Miscellaneous -

 16. Date and venue for next meeting -


  (MBa) Mark Baker          Univ. of Portsmouth
  (MBe) Michael Berry       Univ. of Tennessee
  (JD)  Jack Dongarra       Univ. of Tenn./ORNL
  (RE)  Rudi Eigenmann      SPEC
  (VG)  Vladimir Getov      Univ. of Westminister
  (TH)  Tony Hey            Univ. of Southampton
  (AH)  Adolfy Hoisie       LLNL
  (SS)  Subhash Saini       NASA Ames
  (RS)  Ron Sercely         HP/CXTC
  (ES)  Erich Strohmaier    Univ. of Tennessee


Jack Dongarra
Erich Strohmaier


From owner-parkbench-comm@CS.UTK.EDU Tue May  6 14:46:45 1997
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Date: Tue, 6 May 1997 19:06:15 +0100
To: parkbench-comm@CS.UTK.EDU
From: Roger Hockney <roger@minnow.demon.co.uk>
Subject: Parkbench Meeting Documents
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AGENDA ITEM:

>     Changes to Current release:
>  2. Low Level (VG)
>     comms1, comms2,

Two documents will be submitted to the committee on this item by Roger
Hockney and Vladimir Getov (Westminster University, UK). They can be
downloaded as postscript files from:

"New COMMS1 Benchmark: Results and Recommendations"
http://www.minow.demon.co.uk/Pbench/comms1/PBPAPER2.PS
 
"New COMMS1 Benchmark: The Details"
http://www.minow.demon.co.uk/Pbench/comms1/PBPAPER3.PS

The papers will be presented by Vladimir who will bring some paper
copies with him.

Best wishes
Roger and Vladimir
-- 
Roger Hockney.  Checkout my new Web page at URL   http://www.minnow.demon.co.uk
University of   and link to my new book: "The Science of Computer Benchmarking"
Westminster UK  suggestions welcome. Know any fish movies or suitable links?

From owner-parkbench-comm@CS.UTK.EDU Tue May  6 17:54:47 1997
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Date: Tue, 6 May 1997 21:26:50 +0100
To: parkbench-comm@CS.UTK.EDU
From: Roger Hockney <roger@minnow.demon.co.uk>
Subject: Parkbench Meeting Documents (Correction)
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I am resending this because there was a typo in the URLs:
There are two MM in "minnow". 

Also if you took PBPAPER2.PS before receiving this repeat message,
please take it again as I have corrected two errors in the graphs.

SORRY 
Roger
************************
AGENDA ITEM:

>     Changes to Current release:
>  2. Low Level (VG)
>     comms1, comms2,

Two documents will be submitted to the committee on this item by Roger
Hockney and Vladimir Getov (Westminster University, UK). They can be
downloaded as postscript files from:

CORRECTED URLs:

"New COMMS1 Benchmark: Results and Recommendations"
http://www.minnow.demon.co.uk/Pbench/comms1/PBPAPER2.PS
              
"New COMMS1 Benchmark: The Details"
http://www.minnow.demon.co.uk/Pbench/comms1/PBPAPER3.PS

The papers will be presented by Vladimir who will bring some paper
copies with him.

Best wishes
Roger and Vladimir
-- 
-- 
Roger Hockney.  Checkout my new Web page at URL   http://www.minnow.demon.co.uk
University of   and link to my new book: "The Science of Computer Benchmarking"
Westminster UK  suggestions welcome. Know any fish movies or suitable links?

From owner-parkbench-comm@CS.UTK.EDU Mon May 12 05:36:41 1997
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From: Pat Worley <worley@haven.EPM.ORNL.GOV>
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To: parkbench-comm@CS.UTK.EDU
Subject: Gordon Conference on HPC and NII 
Forwarding: Mail from 'Tony Skjellum <tony@aurora.cs.msstate.edu>'
     dated: Sat, 10 May 1997 16:32:12 -0500 (CDT)
Cc: worley@haven.EPM.ORNL.GOV

Just in case you haven't received information on this already, here is a
blurb on the 1997 Gordon conference in high performance computing. 
Unlike previous years, there is not an explicit emphasis on performance
evaluation in this year's stated themes, but you can't (shouldn't) discuss
future architectures and their impacts without discussing how to
evaluate performance, and I am hoping that some benchmarking-minded people
will show up and keep the discussion honest.

---------- Begin Forwarded Message ----------

The deadline for applying to attend the 1997 Gordon conference in high
performance computing is June 1. If you are interested in attending,
please apply as soon as possible. The simplest way to apply is to download
the application form from the web site indicated below, or to use the online
registration option. If you have any problems with either of these,
please contact the organizers at tony@cs.msstate.edu and worleyph@ornl.gov.

-------------------------------------------------------------------------------
The 1997 Gordon Conference on High Performance Computing and
Information Infrastructure: "Practical Revolutions in HPC and NII"

Chair, Anthony Skjellum, Mississippi State University, tony@cs.msstate.edu,
       601-325-8435
Co-Chair, Pat Worley, Oak Ridge National Laboratory, worleyph@ornl.gov,
       615-574-3128

Conference web page: http://www.erc.msstate.edu/conferences/gordon97

July 13-17, 1997
Plymouth State College
Plymouth NH

The now bi-annual Gordon conference series in HPC and NII commenced in 1992
and has had its second meeting in 1995.  The Gordon conferences are an
elite series of conferences designed to advance the state-of-the-art in
covered disciplines. Speakers are assured of anonymity and
referencing presentations done at Gordon conferences is prohibited by
conference rules in order to promote science, rather than publication
lists.  Previous meetings have had good international participation,
and this is always encouraged. Experts, novices, and technically
interested parties from other fields interested in HPC and NII are
encouraged to apply to attend.

All attendees, including speakers, poster presenters, and session chairs
must apply to attend. We *strongly* encourage all poster presenters to have
their poster proposals in by May 13, 1997, though we will consider poster
presentations up to six weeks prior to the conference.  Application to
attend the conference is also six weeks in advance.

More information on the conference can be found at the web page
listed above, including the list of speakers and poster presenters
and information on applying for attendance.


----------- End Forwarded Message -----------


From owner-parkbench-comm@CS.UTK.EDU Tue May 13 13:58:00 1997
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Subject: Parkbench directions
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To:   ParkBench Group
From: Charles Grassl

Date: May 13, 1997

(Long)

I appreciated the meeting this past week and wish to thank Eric and Jack 
for hosting it.  I am aware of the great effort of many individuals
have contributed to developing and implementing the ParkBench suite.
In spite of this, I feel that we need to evaluate and correct our course.

ParkBench should not merge with or use benchmarks from the SPEC/HPG
(High Performance Group) group.  SGI/Cray and IBM have already
withdrawn from the SPEC/HPG group and Fujitsu and NEC are no longer
participating.  The reasons for these companies and other institutions
no longer participating should indicate to us (ParkBench) that
something is amiss with the SPEC/HPG benchmarks and paradigm.

Several of the reasons for the supercomputer manufacturers not
supporting the SPEC/HPG effort are listed below.  I list these reasons
so that the ParkBench group can learn from them and avoid the same
problems.

- Relevance.  The particular benchmark programs being used by SPEC/HPG
  are not relevant or appropriate for supercomputing.  The programs in
  the current SPEC/HPG suite do not represent any leading edge software
  which is more typical of usage for high performance systems.

- Redundancy.  The programs being developed by SPEC/HPG
  are not qualitatively or quantitatively different from the SPEC/OSG
  programs and as such, it is viewed as redundant and expensive.

- Methodology.  The methodology being used by SPEC/HPG to
  procure, develop and run benchmarks lacks scientific and technical
  basis and hence results have a vague and arbitrary interpretation.

- Programming model.  Designing benchmarks for portability across
  systems is a convenient idea but does not reflect actual constraints
  or usage.  More often than not, compatibility with a PREVIOUS model
  of computer is more important than compatibility ACROSS computers.

- Expense.  Some of the large data cases for the SPEC/HPG programs
  will requires hours or days to run with little new data or
  information gained by the exercise.  These exercises are extremely
  expensive both in time and capital equipment and in logistics.

- Ergonomics.  The cumbersome design of SPEC/HPG Makefiles and build
  procedures make the programs difficult and expensive to test,
  maintain and analyze.

We in the ParkBench group must acknowledge the above items if we are to
maintain interest and participation from computer vendors.  I believe
that reorganizing and refocusing the group could revitalize high
performance computer benchmarking and and re-invigorate the ParkBench
group.

As the ParkBench suite now stands, there are too many programs and they
are difficult to build, test and maintain.  This situation impedes
usage and participation.  Here are a few suggestions for our future
practices and directions:

- Design and write benchmarks programs.  Don't borrow or solicit old
  code.  The borrowed or solicited code is never quite appropriate and
  usually obsolete.  Our greatest asset is that we have scientist who
  are capable of designing experiments (benchmarks).  (Build value.)

- Monitor and evaluate accuracy.  Though we mention accuracy in
  ParkBench Report 1, we haven't applied it to the current programs
  (Scientifically validate, or invalidate, our experiments.)

- Make it simple.  Write and develop simple programs which do not need
  elaborate build procedures and which easier to test and to maintain.
  (Keep It Simple, Stupid.)

- Build a better user interface.  The belabored "run rules" and the
  interface with layers of Makefiles, includes and embedded relative
  file paths is unacceptable.  An acceptable interface might require
  binary distribution and hence a desirable emphasis on designing and
  running rather than building and porting the benchmarks.  (Make the
  product more attractive to more users.)

- Make the suite truly modular.  The current structure makes the
  simplest one CPU program as difficult to build and run as the most
  complicated program with Makefile includes, special compilers, source
  file includes, special libraries, suite libraries, etc. (Make it
  manageable.)

- Drop the connection with SPEC/HPG and with NPB.  This "grand
  unifying" scheme make redundant code.  It has had the opposite effect
  of focusing benchmarking attention on ParkBench because it is yet
  another collection of benchmarks used by other organizations.  (Be
  distinguishable and identifiable.)

- Emphasis what ParkBench is associated with:  benchmarking distributed
  memory parallel computers.  We should write and develop benchmark
  programs which measure and instrument the parallel processing aspect
  of MPP systems.  (Keep our focus.)


I volunteer to develop and write a suite of message passing test
programs which measure the performance and variance of message passing
communication schemes.  I have much experience with writing such a
programs and believe that such suite would be useful for others and for
the computer industry in general.

I hesitate to contribute such programs to the present structure for
several reasons:

- The network test suite does not logically fit into the current
  "hierarchy" and hence might further clutter the ParkBench suite and
  make it further unfocused.

- The current ParkBench structure is not manageable.  Testing and
  maintenance would be extremely expensive in the current structure.

- My company's effort may be interpreted as an endorsement of the
  current structure and model.  The suite is not popular with vendors
  for reasons outlined above.  Participation is currently discouraged.


Discussion?  


Regards,
Charles Grassl
SGI/Cray
Eagan, Minnesota  USA

From owner-parkbench-comm@CS.UTK.EDU Wed May 21 17:25:15 1997
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Date: Wed, 21 May 1997 17:24:42 -0400
From: "Philip J. Mucci" <mucci@CS.UTK.EDU>
Organization: University of Tennessee, Knoxville
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CC: "PVM Developer's Mailing List" <pvmspankers@msr.epm.ornl.gov>
Subject: Mesg Passing Benchmarks
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Hi all,

Charles Grassl in his last message to this committee volunteered
to write a suite of message passing benchmarks to replace the Low
Levels...Before any action on his or this committee's part, I would
recommend that you all have a look at version 3 of my pvmbench
package. It now does MPI as well and can easily support other
message passing primitives with a few #defines. 

Version 3 along with some sample results can be found at
http://www.cs.utk.edu/~mucci/pvmbench.

Note that this has not been tested on any MPP's with UTK PVM.

This benchmark will generate and graph the following:

bandwidth
gap time (to buffer an outgoing message)
roundtrip (latency /2)
barrier/sec
broadcast
summation reduction

Other tests can easily be added...I would highly recommend before any 
action done that this code be examined. It is less than a year old, 
version 3 available on that page is in beta, i.e. it has not been
released to the general public. Let me know what you think...

-Phil

-- 
/%*\ Philip J. Mucci | GRA in CS under Dr. JJ Dongarra /*%\
\*%/ http://www.cs.utk.edu/~mucci  PVM/Active Messages \%*/

From owner-parkbench-comm@CS.UTK.EDU Fri May 23 12:03:04 1997
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to: parkbench-comm@CS.UTK.EDU
Subject: Minutes of May ParkBench Meeting
Date: Fri, 23 May 1997 11:05:31 -0400
From: "Michael W. Berry" <berry@CS.UTK.EDU>

Here are the minutes from the recent ParkBench meeting in Knoxville.
Best regards,
Mike

-----------------------------------------------------------------
Minutes of ParkBench Meeting - Knoxville Hilton, May 9, 1997
-----------------------------------------------------------------

ParkBench Attendee List:

     (MBa) Mark Baker          Univ. of Portsmouth   mab@sis.port.ac.uk
     (MBe) Michael Berry       Univ. of Tennessee    berry@cs.utk.edu
           Shirley Browne      Univ. of Tennessee    browne@cs.utk.edu
     (JD)  Jack Dongarra       Univ. of Tenn./ORNL   dongarra@cs.utk.edu
           Jeff Durachta       Army Res. Lab MSRC    durachta@arl.mil
     (VG)  Vladimir Getov      Univ. of Westminister getovv@wmin.ac.uk
     (CG)  Charles Grassl      SGI/Cray              cmg@cray.com
     (TH)  Tony Hey            Univ. of Southampton  ajgh@ecs.soton.ac.uk
     (AH)  Adolfy Hoisie       Los Alamos Nat'l Lab  hoisie@lanl.gov
     (CK)  Charles Koelbel     Rice University       chk@cs.rice.edu
     (PM)  Phil Mucci          Univ. of Tennessee    mucci@cs.utk.edu
           Erik Riedel         GENIAS Software GmbH  erik@genias.de
     (SS)  Subhash Saini       NASA Ames             saini@nas.nasa.gov
     (RS)  Ron Sercely         HP-Convex             sercely@convex.hp.com
           Alan Stagg          CEWES                 stagga@wes.army.mil
     (ES)  Erich Strohmaier    Univ. of Tennessee    erich@cs.utk.edu
     (PW)  Pat Worley          Oak Ridge Nat'l Lab   worleyph@ornl.gov

SPEC-HPG Visitors:

           Don Dossa           DEC                   dossa@eng.pko.dec.com
     (RE)  Rudi Eigenmann      Purdue University     eigenman@ecn.purdue.edu
           Greg Gaertner       DEC                   ggg@zko.dec.com
           Jean Suplick        HP                    suplick@rsn.hp.com
           Joe Throp           Kuck & Associates     throp@kai.com

At 9:05am EST, TH opened the meeting and ask that all the attendees
introduce themselves.  After a brief overview of the proposed agenda,
MBe reviewed the minutes from the last ParkBench meeting in October
of '96.  The minutes were unanimously accepted and TH asked VG to
present the proposed changes to the low-level benchmarks (9:20am).

VG reviewed the original COMMS1 (ping-pong or simplex communication) and
the COMMS2 (duplex communication) low-level benchmarks.  He discussed
some of the problems with the previous versions.  These included the
omission of calculated bandwidth, large message length problems, and
large errors in the asymptotic fit.   In collaboration with RS and CG,
a number of improvements have been made to these benchmarks:

	1. Measured bandwidth is provided in output.
	2. Time for shortest message is provided.
	3. Maximum measured bandwidth and the corresponding message
	   length is now provided.
	4. The accuracy of the least-squares 2-parameter fit has been
	   improved (sum of squares of the "relative" and not absolute
	   error is now used).
	5. New 3-parameter variable-power fit for certain cases added.
	6. Can report parametric fits if the error is less than some
   	   user-specified tolerance.
	7. Introduce KDIAG parameter to invoke diagnostic outputs.
	8. Modifications fo ESTCOM.f (as suggested by RS).
    
CG pointed out that it may not always be possible to interpret zero-length 
messages for these codes.  On the Cray machines, such messages force an 
immediate return (i.e., no synchronization).  He proposed that allowing zero-
length messages be removed for the COMMS benchmarks.  RS showed an actual
COMMS1 performance graph demonstrating the difficulty of data extrapolation
(if used to get latency for zero-length message-passing).  RS pointed out,
however, that zero-length message are defined w/in MPI, and suggested that
a simple return (as in the case of Cray machines) is not standard.

VG displayed some of the observed COMMS1/2 performance obtained on the
Cray T3E.  The 3-parameter fit yielded a 7% relative error for messages
ranging from 8 to 1.E+7 bytes.  CG questioned how the breakpoints were
determined?  He indicated the input parameters to the program required
previous knowledge of where breakpoints occur (although implementations
could change constantly).  TH suggested that the parametric fitting should
not be the default for these benchmarks, i.e., separate the analysis from
the actual benchmarking (this concept was seconded by CG).  RS suggested
that the fitting routines could be placed on the WWW/Internet and the
COMMS1/2 codes simply produce data.  CK, however, stressed that the codes
should maintain some minimal parametric fitting for clarity and
consistency of output interpretations.  

The minimal message length shown for the T3E results shown by VG was 8 and
the corresponding minimal message length for a Convex CXD set of
COMMS benchmarks was 1.  The lack of similar ranges of messages could
pose problems for comparisons.  JD strongly felt that users will return
to the notion of "latency" and want zero-length message overheads.  Users
may be primarily interested in start-up time for message-passing.  RS pointed
out that MPI does process zero-length messages.  JD suggested that
the minimal message length for the COMMS benchmarks be 8 bytes and RS proposed
that the minimal message-passing time and corresp. message length be
an output.  After more discussion, the following COMMS changes/outputs were 
unanimously agreed upon:

	1.  Maximum bandwidth with corresp. message size.
	2.  Minimum message-passing time with corresp. message size.
	3.  Time for minimum message length (could be 0, 1, 8, or 32 bytes
            but must be specified).
	4.  The software will be split into two program: one to report
	    the spot measurements and the other for the analysis.


At 10:00 am, SPEC-HPG members joined the ParkBench meeting for a joint
session.  CK reviewed the DoD Modernization Program.  He indicated that
the program is based on 3 primary components:

	1. CHSSI (Commonly Highly Scalable Software Initiative)
	2. DREN (Defense Research & Engineering Network)
	3. Shared Resource Centers (4 Major Shared Resource Centers or
           MSRC's and 20 Distributed Centers or DC's)

Benchmarking is part of the mission of the MSRC's, especially for
system integration and the Programming Environment & Training (PET)
team.  CK mentioned that the resources available at the MSRC's include:

256-proc. Cray T3E, SGI Power Challenge (CEWES), 256 proc. IBM SP/2 and
SGI Origin 2000 at ASC, SGI 790 at NAVO, and a collection of {SGI Origin,
Cray Titan, J90} at the Army Research Lab.

The benchmarking needs of the DoD program can be categorized as either
contractual or training.  The contractual needs are specified as PL1
(evaluation of initial machines), PL2 (upgrade to gain 3 times the
performance of PL1), and PL3 (upgrade to gain 10 times the performance
of PL1).  CK mentioned that the MSRC's are planning for the PL2 phase
later this year with PL3 scheduled in approx. 3 years.
The training needs include: the evaluation of programming paradigms,
the evaluation of performance trade-offs, templates for designing new
codes, and benchmarks for training examples.

The contractual benchmarks comprise 30 benchmarks (22 programs) some
of which are export-controlled or proprietary (data may not be used
in the public domain in some cases).  The run rules specify the number
of iterations for each benchmark in the suite.  Each MSRC uses a different
number of iterations per benchmark.  Code modifications are allowed (parallel
directives and message-passing can be used but no assembler) and algorithm
substitutions are permitted provided the problem does not become specialized.
The only performance metric reported for these benchmarks is the elapsed
time for the entire suite.  Benchmarks can be upgraded to reflect current
workloads of the MSRCs but they must be compared head-to-head with 
previous systems.

Example codes included in the DoD benchmark suite include: CTH (finite
volume shock simulation), X3D (explicit finite element code), OCEAN-O2 (an
ocean modeling code), NIKE3D (implicit nonlinear 3D FEM), and Aggregate
I/O benchmark.

Planned benchmarking activites for the DoD Modernization Program include:

	1. benchmarks for evaluating programming techniques (determine what
           works; develop decision trees)
	2. benchmarks for teaching (classes on "worked" examples; template
           modification)

This effort currently has 1 FTE and over 50 University personnel (in PET
program) involved (although they are not primarily responsible for
benchmarking work).

At 10:35am, TH asked AH from Los Alamos Nat'l Lab to overview their ASCI
benchmark suite.  He began by pointing out that these codes formulate the
"Los Alamos set of" ASCI Benchmarks.  Before presenting the list of codes,
AH noted that the philosophy of this activity was to achieve 
"experiment ahead" capability especially with immature computing platforms.
Los Alamos is also interested in developing performance modes as well as
kernels.  The list of active/research codes and compact applications 
comprising this suite are:

Code		Language(s)	Parallelism 	Description           
    
*HEAT(RAGE)	f77, f90	MPI(f90)	Eulerian adaptive mesh
				MPIfSM(f77)	refinement based on
						Riemann solvers; coupled
						physics-CFD; particle &
						radiative transport

EULER		f90		MPI		Admissable fluid (for SIMD);
				SIMD(SP		unstructured mesh, explicit
				vector)		solution; high-speed fluids;
						SP=single processor

NEUT		f77		MPI,SM,		Monte-Carlo, particle
				SHMEM

SWEEP3D		f90		MPI, SHMEM	Inner/outer iteration (kernel)
                                                (compact application)

HYDRO(T)	f77		Serial          (compact application)

TBON		f77		MPI		Material science; quantum
						mechanics; polymer age    
						simulation

*TECOLOTE	C++		MPI		Mixed call hydro. with regular
						structured grid

*TELURIDE	f90		MPI		Casting simulation; irregular
						structured grid; Krylov solution
						methods

*DANTE		HPF		MPI

* = export controlled

The codes and compact apps above vary in size from 2,000 to 35,000 lines.
AK noted that LANL could provide support for future ASCI-based ParkBench codes. 
The ASCI benchmark suite presented might include in the future tri-lab
(Livermore, Sandia, Los Alamos) contributions.  The ASCI application suite can
be set up with data sets leading to varying run-times.  AH mentioned that Los 
Alamos' ASCI benchmarking efforts are focused on high performance computing,
leading edge architectures, algorithms, and applications.  They are 
particularly concentrating in developing expertise in distributed shared-memory
performance evaluation and modeling.  AH expressed the hope that the efforts of
ParkBench will follow similar directions.

At 11:05am, SS reviewed some of the most recent NAS Parallel Benchmarks results.
He began with vendor-optimized CG Class B results using row and column 
distribution blocking.  Results for different numbers of processors of the T3D 
were reported along with results for the NEC SX-4, SGI Origin 2K, Convex SPP2K,
Fujitsu VPP700, and IBM P2SC.  He also showed results for FT Class B and BT 
Class B (all machines reported performed well on this benchmark).  For BT, it 
was pointed out that 4 of the machines (Cray T3E, DEC Alpha, IBM P2SC, and NEC 
SX-4) essentially are based on the same processor but achieve widely-varying
results.  SS also reported HPF Class A MG results on 16 processors of the IBM 
SP2.  The HPF version (APR-HPF/Portland Group compiled) was only 3 times slower
than the MPI-based (f77) implementation.  This is indeed a significant result 
given that two years ago the HPF version was as much as 10 times slower than 
the comparable MPI version.  An HPF version of the Class A FT benchmark on 64 
processors was shown to be faster than the MPI version (1.6 times faster) when
optimized libraries are used in both versions.  For the Class A SP benchmark
(on 64 processors of the SP/2), the APR- and PGI-compiled HPF versions were 
within a factor of 2 of the MPI versions.  Finally, the HPF Class A BT code on 
64 processors of the Cray T3D was within a factor of 0.5 of the MPI version.

At 11:35am, TH invited RE to overview current SPEC-HPG activities.  The SPEC-HPG
benchmarks define a suite of real-world high-performance computing applications
designed for comparisons across different platforms (serial and message-
passing).  RE pointed out the history of the SPEC-HPG effort as a merger between
the PERFECT and SPEC benchmarking activities.  The current SPEC-HPG suite is
comprised of 2 codes: SPECchem96 and SPECseis96.  The SPECchem96 code evolved
from the GAMES code used in pharmaceutical and chemical industries.  It
comprises 109,389 lines of f77 (21% comments), 865 subroutines and
functions.  The wave functions are written to disk.  The SPECseis96 code
is derived from the ARCO benchmark suite which consists of four phases: data
generation, stack data, time migration, and depth migration.  This code
decomposes the domain into n equal parts (for n processors) with each part
processed independently.  It is have over 15K lines of code made up of
230 Fortran subroutines and 199 C functions for I/O and systems utilities.
SPECseis96 uses 32-bit precision, FFT's, Kirchoff integrals, and finite
differences.

The very first set of SPEC-HPG benchmark results were approved on May 8,
1997 (preceding day).  New benchmarks being considered are PMD (Parallel
Molecular Dynamics) and MM5 (NCAR Weather Processing C code).  The decision
on whether or not to accept these two potential SPEC-HPG codes will be made
in about 5 months.  The SPEC-HPG run rules permit the use of compiler
switches, source code changes, optimized libraries (which have been
disclosed to customers).  Only approved algorithmic changes will be disclosed.
RE gave the URL for the SPEC-HPG effort: http://www.specbench.org/hpg.  He
also referred to a recent article by himself and S. Hassanzadeh in "IEEE
Computational Science & Engineering" and two email reflectors for SPEC-HPG
communication: comments@specbench.org and info@specbench.org.

JD then gave a brief history of ParkBench and SPEC-HPG interactions and
suggested that the two efforts might consider sharing results and software.
The biggest difference in the two efforts is in the availability of
software as ParkBench code is freely available and SPEC-HPG software
has some restrictions.  A forum to publish both sets of results was discussed
and it was agreed that both efforts should at least share links on their
respective webpages.  RE pointed out that anyone can get the SPEC-HPG CD
of benchmarks without actually being a SPEC member.

JD stressed that the process of running codes (for any suite) needs to
be simplified so that building executables for different platforms is not
problematic.  Modifications for porting should be restricted to driver programs.
RS indicated that he has Perl scripts that runs all low_level, including 
COMMS3 for 2 to N procs, and produces a summary of the results. 

*** ACTION ITEM ***
JD, RE, AH, and CK will discuss a potential joint effort to simplify the
running of benchmark codes (contact RS also about his Perl scripts).

MBa noted that the SPEC-HPG members should be added to the ParkBench
email list (parkbench-comm@cs.utk.edu).  He also indicated that European
benchmarking workshop scheduled next Fall might coordinate with the
European SPEC group (scheduled for Sept. 11-12).

At 12:10pm, the attendees went to the lunch (Soup Kitchen).

After lunch (1:30pm), TH asked ES and VG to coordinate changes to the
COMMS benchmarks discussed above (*** ACTION ITEM ***).  ES then discussed
modifications to poly2 for the ParkBench V2.2 suite.  The proposed changes
include
	1. enlarged arrays A(1000000), B(1000000)
	2. removal of arrays C and D
	3. avoid cache flush (use a sliding vector), i.e., 

             DO I=1,N               DO I=NMIN,NMAX
                         becomes       ...

                                       NMIN=NMIN+N+INC

           where INC=17 by default (avoids reuse of the old cache line).

PM then discussed a program for determining parameters for memory subsystems.
Characteristics of this software include the use of tight loops, independent
memory references, maximized register use.  He showed graphs of memory
hierarchy bandwidth (reads and writes) depicting memory size (ranging from 4Kb
to 4Mb) versus Mb/sec transfer rates.  Some curves illustrated the effective 
cache size quite well.  PM pointed out that dynamically-scheduled processors
pose a significant problem for this type of modeling.  The program can be
run with or without a calibration loop exploiting known memory transfer data.
CG suggested that it would be nice to have such a program to measure latency
at all levels of the hierarchy.  PM's webpages for this program are:

	http://www.cs.utk.edu/~mucci/cachebench and
	http://www.cs.utk.edu/~mucci/parkbench.

CK suggested that an uncalibrated version of PM's benchmark would be more
useful to users (more reflective of real codes).  JD pointed out that the
output of the program could be tabulated bandwidths, latencies, etc.  CG
felt this program would be a very useful tool.  PM noted that the calibration
will not be used by default.  TH suggested that the ParkBench effort might
want to develop a future "ParkBench Tool Set" which contains progams like
this one developed by PM.

With regard to the Linalg Kernels, ES noted that although many of the
routines have calls to Scalapack routines, Scalapack will not be included
in future software releases.  Users will have to ge their own copies of
the source (or binaries) for Scalapack.  The size of these particular
kernel benchmarks drops by a factor of one-third by removing Scalapack.

*** ACTION ITEM ***
ES will report the most recent Linalg benchmark performance results at the
next ParkBench meeting.

TH then asked for discussions on new benchmarks with MBa leading the
discussion on HPF benchmarks.  MBa indicated that a new mail reflector
(parkbench-hpf@cs.utk.edu) had been set up for this cause with himself
as moderator for low-level codes (CK will moderate kernels and SS will
moderate discussions on HPF compact applications).  MBa noted that there
is limited manpower for the HPF benchmarking activities.  CK noted that
he had discussed this effort at recent the HPFF meeting (and other
users meetings).  A draft document on the ParkBench HPF benchmarks is
available at http://www.sis.port.ac.uk/~mab/ParkBench.  MBa felt strongly
that without manpower support this particular activity will die and that
a lead site is needed.

*** ACTION ITEM ***
CK and SS will investigate interest in HPF compact application development.

JD indicated that wrappers are being used to create HPF versions of the
Linalg kernels.  The procedure involves writing wrappers for the current
Scalapack driver programs.  Eventually, these programs may be completely
rewritten in HPF (this will start in the summer).  TH suggested that HPF
kernel benchmark performance be reported at the ParkBench meeting 
in September (at Southampton Performance Workshop).

MBa went on to report on the status of I/O benchmarks.  Basically, not
much progress has been made on the ParkBench I/O initiative.  A new I/O 
project between ECMWF, FECIT, and the Univ. of Southampton was launched
this past February.  They are looking at the I/O  in the IFS code from
the ECMWF (European Weather Forecasting).  David Snelling is the FECIT
leader who has also participated in ParkBench activities.  This I/O
project has 1 FTE at Southampton and 1.5 FTE at FECIT along with several
personnel at ECMWF.  One workshop, two technical meetings for the 1-year
project is planned.  The goals are: to develop instrumented I/O
benchmarks and build on top of MPI-IO (test, characterize parallel
systems).  Their methodology is very similar to that of ParkBench.
Codes in f90 and ANSI C are being considered (stubs for VAMPIR and
PABLO).  Regular reports to Fujitsu (sponsor of activity) are planned
and a full I/O test suite is planned by February 1998.

MBa also reported on the status of the ParkBench graphical database.
Currently, the performance data is kept in a relational DBMS.  A
frontend Java applet has been written to query the DBMS on-the-fly.
A backend is also in development which will automate the extraction
of new performance data and insertion into the DBMS (via an http
server).  By September, a more complete prototype which will allow
MS access and JDBC between 2 different machines should be ready.

VG then discussed the development of Java-based low-level benchmarks.
He presented a Java-to-C Interface Generator which would allow Java
benchmarks to call existing C libraries on remote machines.  He
presented sample Java+C NAS PB results on a 16-processor IBM SP/2
(Class A IS Benchmark):

           Version        1 Proc  2Procs  4 Procs  8 Procs  16 Procs
           NASA (C)        29.1    17.4     9.4     5.2        2.8
                 C         40.5    24.9     13.1    9.3       15.6
              Java         ----   132.5     64.7   37.9       33.5

At 2:50pm, TH reported other ParkBench activities including the
new PEMCS (Performance Evaluation and Modeling for Computer Systems)
electronic journal.  Suggested articles/authors include:

       *1. ParkBench Report No. 2 (ES, MBe)
       *2. NAS PB
	3. SPEC-HPG
       *4. Top 500
	5. AutoBench (M. Ginsburg)
       *6. Euroben (van der Steen)
	7. RAPS
	8. Europort
       *9. Cache benchmarks
       10. ASCI benchmarks (DoD)
      *11. PERFORM
       12. R. Hockney
      *13. PEPS
       14. C3I/Rome Labs

Those articles possible for Summer '97 are marked via *.  JD suggested
that articles be available in Encapsulated Postscript, PDF (Adobe),
and HTML.  TH noted that EU funding will provide a host computer and
some administration.  Possible publishers are Oxford Univ. Press and
Elsevier.

At 3:10pm, ES requested more items for the ParkBench bibliography
which will be available on the WWW.  PW suggested that authors should
be able to submit links to ParkBench-related applications.  JD then
briefly discussed WebBench which is a website focused on benchmarking
and performance evaluation.  Data is presented on platform,s applications,
organizations, vendors, conferences, papers, newsgroups, FAQ's, and
repositories (PDS, Top500, Linpack, etc.).  The WebBench URL is
http://www.netlib.org/benchweb.

MBa reminded attendees of the Fall Performance Workshop/ParkBench
meeting on (Thursday and Friday) Sept. 11 and 12.  This meeting
will be held at Venue, County Hotel, Southampton, UK.  Invited
and contributed talks will be presented.

With regard to ParkBench funding, JD indicated that the UT/ORNL/NASA
Ames proposal was not selected for funding but that it could be re-
submitted next year.  Expected funding from Rome lab was not received.
TH and VG did not succeed this past year either although some funding
from Fujitsu is possible.

TH adjourned the meeting at 3:25pm EST.

From owner-parkbench-comm@CS.UTK.EDU Tue May 27 10:32:45 1997
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From: maira@inf.puc-rio.br (Maira Tres Medina)
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Date: Tue, 27 May 1997 11:10:58 -0300
Message-Id: <199705271410.LAA16226@obaluae>
To: parkbench-comments@CS.UTK.EDU
Subject: Benchmarks
Cc: parkbench-comm@CS.UTK.EDU, maira@CS.UTK.EDU, victal@CS.UTK.EDU
X-Sun-Charset: US-ASCII

Hello 

I'm a graduate student at the Computer Science Department of PUC-Rio
(Catholic University of Rio de Janeiro). I'm  currently studing
Low_Level benchmarks for measuring basic computer characteristics.

I have had same problems trying to run some of the benchmarks.
For example, the benchmark comms1 for PVM, prints the following errors messages
and stops.
 
    n05.sp1.lncc.br:/u/renata/maira/ParkBench/bin/RS6K>comms1_pvm
      Number of nodes =          2
      Front End System (1=yes, 0=no) =          0
      Spawning done by process (1=yes, 0=no) =          1
      Spawned           0  processes OK...
      libpvm [t4000c]: pvm_mcast(): Bad parameter
      TIDs sent...benchmark progressing...
 
 
   n05.sp1.lncc.br:/u/renata/maira/ParkBench> bin/RS6K/comms1_pvm 
     1525-006 The OPEN request cannot be processed because STATUS=OLD was coded 
     in the OPEN statement but the file comms1.dat does not exist. The program 
     will continue if ERR= or IOSTAT= has been coded in the OPEN statement.
     1525-099 Program is stopping because errors have occurred in an I/O request 
     and ERR= or IOSTAT= was not coded in the I/O statement.
 
 
I would like to know how I can execute the benchmarks only for  PVM.
Can you help me?
 
I have not had problems with benchmarks sequentials (tick1, tick2 ...).
 
Thank you very much for your attention.
 
Maira Tres Medina
Phd. Student
Pontificial Catholic University
Rio de Janeiro, Brazil
 

From owner-parkbench-comm@CS.UTK.EDU Wed May 28 16:36:07 1997
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Date: Wed, 28 May 1997 16:33:33 -0400
From: "Philip J. Mucci" <mucci@CS.UTK.EDU>
Organization: University of Tennessee, Knoxville
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To: Maira Tres Medina <maira@inf.puc-rio.br>
CC: parkbench-comments@CS.UTK.EDU, parkbench-comm@CS.UTK.EDU
Subject: Re: Benchmarks
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Hi,

You need to make sure the dat files are in the executable directory.
They should be installed in $PVM_ROOT/bin/$PVM_ARCH.

-Phil

-- 
/%*\ Philip J. Mucci | GRA in CS under Dr. JJ Dongarra /*%\
\*%/ http://www.cs.utk.edu/~mucci  PVM/Active Messages \%*/

From owner-parkbench-comm@CS.UTK.EDU Thu Jun  5 11:30:41 1997
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From: Pat Worley <worley@haven.EPM.ORNL.GOV>
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To: parkbench-comm@CS.UTK.EDU
Subject: Gordon conference deadline extended
Forwarding: Mail from 'Pat Worley <worley>'
     dated: Thu, 5 Jun 1997 10:48:07 -0400 (EDT)
Cc: worley@haven.EPM.ORNL.GOV, tony@cs.msstate.edu

(Our apologies if you receive this multiple times.)

There is still room for additional attendees at the Gordon Conference on High
Performance Computing, and the Gordon Research Conference administration has
agreed to extend the application deadline. As a practical matter,
applications need to be submitted no later than JULY 1. We will also stop
accepting applications before that date if the maximum meeting size is
reached, so please apply as soon as possible if you are interested in
attending.   

The simplest way to apply is to download the application form from the web
site 

http://www.erc.msstate.edu/conferences/gordon97

or to use the online registration option available at the same site.
If you have any problems with either of these, please contact the organizers
at tony@cs.msstate.edu and worleyph@ornl.gov. 

Complete information on the meeting is available from the Web site or its
links, but a short summary of the meeting follows:

--------------------------------------------------------------------------

The 1997 Gordon Conference on High Performance Computing and
Information Infrastructure: "Practical Revolutions in HPC and NII"

Chair, Anthony Skjellum, Mississippi State University, tony@cs.msstate.edu,
       601-325-8435
Co-Chair, Pat Worley, Oak Ridge National Laboratory, worleyph@ornl.gov,
       615-574-3128

Conference web page: http://www.erc.msstate.edu/conferences/gordon97

July 13-17, 1997
Plymouth State College
Plymouth NH

The now bi-annual Gordon conference series in HPC and NII commenced in 1992
and has had its second meeting in 1995.  The Gordon conferences are an
elite series of conferences designed to advance the state-of-the-art in
covered disciplines. Speakers are assured of anonymity and
referencing presentations done at Gordon conferences is prohibited by
conference rules in order to promote science, rather than publication
lists.  Previous meetings have had good international participation,
and this is always encouraged. Experts, novices, and technically
interested parties from other fields interested in HPC and NII are
encouraged to apply to attend.

The conference consists of technical sessions in the morning and evening,
with afternoons free for discussion and recreation. Each session consists of
2 or 3 one hour talks, with ample time for questions and discussion. All
speakers are invited and there are no parallel sessions. All attendees are
both encouraged and expected to actively participate, via discussions during
the technical sessions or via poster presentations. 

All attendees, including speakers, poster presenters, and session chairs,
must apply to attend. Poster presenters should indicate their poster
proposals on their applications. While all posters must be approved,
successful applicants should assume that their posters have been accpeted
unless they hear otherwise. 

Meeting Themes:
  Networks: Emerging capabilities and the practical implications
          : New types of networking  
  Real-Time Issues
  Multilevel Multicomputers
  Processors-in-Memory and Other Fine Grain Computational Architectures
  Impact of Evolving Hardware on Applications
  Impact of Software Abstractions on Performance

Confirmed Speakers:
  Ashok K. Agrawala		University of Maryland
  Kirstie Bellman		DARPA/SISTO
  James C. Browne		University of Texas at Austin
  Andrew Chien			University of Illiniois, Urbana-Champaign
  Thomas H. Cormen		Dartmouth College
  Jean-Dominique Decotignie	CSEM
  David Greenberg		Sandia National Laboratories
  William Gropp			Argonne National Laboratory
  Don Heller			Ames Laboratory
  Jeff Koller			Information Sciences Institute
  Peter Kogge			University of Notre Dame
  Chris Landauer		The Aerospace Corporation
  Olaf M. Lubeck		Los Alamos National Laboratory
  Andrew Lumsdaine		University of Notre Dame
  Lenore Mullins		SUNY, Albany
  Paul Plassmann		Argonne National Laboratory
  Lui Sha			Carnegie Mellon Univeristy
  Paul Woodward			University of Minnesota


From owner-parkbench-comm@CS.UTK.EDU Tue Jul  1 17:06:52 1997
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Date: Tue,  1 Jul 97 20:55:49    
From: Mark Baker <mab@sis.port.ac.uk>
Subject: Fall 97 Parkbench Workshop - Southampton, UK
To: ejz@ecs.soton.ac.uk, parkbench-comm@CS.UTK.EDU, parkbench-hpf@CS.UTK.EDU,
        William Gropp <gropp@mcs.anl.gov>,
        Antoine Hyaric <Antoine.Hyaric@comlab.ox.ac.uk>, gent@genias.de,
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Cc: lec@ecs.soton.ac.uk, rjr@ecs.soton.ac.uk,
        "MATRAVERS Prof. D R STAF" <DRM12@sms.port.ac.uk>,
        wilsona@sis.port.ac.uk, grant <grant@afs.mcc.ac.uk>,
        hwyau@epcc.ed.ac.uk
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Dear All,

This is to let you know that the Department of Electronics and Computer
Science at the University of Southampton is organising a Fall 97 
Parkbench Workshop on the 11th and 12th of September 1997.
See http://hpc-journals.ecs.soton.ac.uk/Workshops/PEMCS/fall-97/ for futher 
details.

The workshop will include a number of talks from researchers working in
th field of performance evaluation and modelling of computer systems, a panel
discussion session and a Parkbench committee meeting.

The Workshop is free to attend - workshop delegates need only cover their
own travel and accommodation expenses. Attendance is limited and so the 
availability of places at the Workshop will be allocated on a first come basis.

It is planned to turn the talks given at the Workshop into a series of 
short papers which will be put together and published as a Special Issue 
of the electronic journal Performance Evaluation and Modelling of 
Computer Systems (PEMCS).

For further information or registration details refer to the Web pages -
(http://hpc-journals.ecs.soton.ac.uk/Workshops/PEMCS/fall-97/registration.html).

I would appreciate it if you would kindly pass this email onto colleges who
may be interested in the event.

Regards

Mark


-------------------------------------
Dr Mark Baker
CSM, University of Portsmouth, Hants, UK
Tel: +44 1705 844285	Fax: +44 1705 844006
E-mail: mab@sis.port.ac.uk
Date: 7/1/97 - Time: 8:55:49 PM
URL http://www.sis.port.ac.uk/~mab/
-------------------------------------


From owner-parkbench-comm@CS.UTK.EDU Wed Jul 23 17:19:23 1997
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Date: Wed, 23 Jul 97 22:01:41 +0000
From: Mark Baker  <mab@sis.port.ac.uk>
Subject: PEMCS Web Site
To: parkbench-comm@CS.UTK.EDU, parkbench-hpf@CS.UTK.EDU
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Dear All,

The Web site that will host the Journal of "Performance 
Evaluation and Modelling of Computer Systems (PEMCS)" can
be found at:

http://hpc-journals.ecs.soton.ac.uk/PEMCS/

The pages I have put up are at the present still in a 
"draft/under-construction" state.

I would appreciate any comments or feedback about the
pages.

Regards

Mark



-------------------------------------
Dr Mark Baker
DIS, University of Portsmouth, Hants, UK
Tel: +44 1705 844285	Fax: +44 1705 844006
E-mail: mab@sis.port.ac.uk
Date: 07/23/97 - Time: 22:01:41
URL http://www.sis.port.ac.uk/~mab/
-------------------------------------


From owner-parkbench-comm@CS.UTK.EDU Thu Jul 24 08:26:42 1997
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To: Mark Baker <mab@sis.port.ac.uk>
cc: parkbench-comm@CS.UTK.EDU, parkbench-hpf@CS.UTK.EDU
Subject: Re: PEMCS Web Site 
In-reply-to: Your message of Wed, 23 Jul 1997 22:01:41 -0000.
             <Chameleon.869692062.mab@baker> 
Date: Thu, 24 Jul 1997 08:21:24 -0400
From: "Michael W. Berry" <berry@CS.UTK.EDU>



> Dear All,
> 
> The Web site that will host the Journal of "Performance 
> Evaluation and Modelling of Computer Systems (PEMCS)" can
> be found at:
> 
> http://hpc-journals.ecs.soton.ac.uk/PEMCS/
> 
> The pages I have put up are at the present still in a 
> "draft/under-construction" state.
> 
> I would appreciate any comments or feedback about the
> pages.
> 
> Regards
> 
> Mark
> 
> 
> 
> -------------------------------------
> Dr Mark Baker
> DIS, University of Portsmouth, Hants, UK
> Tel: +44 1705 844285	Fax: +44 1705 844006
> E-mail: mab@sis.port.ac.uk
> Date: 07/23/97 - Time: 22:01:41
> URL http://www.sis.port.ac.uk/~mab/
> -------------------------------------
> 

Mark,
the webpages are well organized.  You might reconsider the
red text on the green background of the menu frame.  It was
difficult to read on my machine at home.

Nice work!
Mike

-------------------------------------------------------------------
Michael W. Berry                     Ayres Hall 114
berry@cs.utk.edu                     Department of Computer Science          
OFF:(423) 974-3838                   University of Tennessee
FAX:(423) 974-4404                   Knoxville, TN  37996-1301
URL:http://www.cs.utk.edu/~berry/
-------------------------------------------------------------------

From owner-parkbench-comm@CS.UTK.EDU Fri Aug  1 12:59:29 1997
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	id AA15842; Fri, 1 Aug 97 17:36:11 BST
Date: Fri,  1 Aug 97 17:17:51 +0000
From: Mark Baker  <mab@sis.port.ac.uk>
Subject: Reminder - Fall Parkbench Workshop
To: parkbench-comm@CS.UTK.EDU, parkbench-hpf@CS.UTK.EDU
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Dear All,

This email is a reminder about the:

----------------------------------------------------------------------------------------------------

				Fall ParkBench Workshop

                           Thursday 11th/Friday 12th September 1997 

                               at the University of Southampton, UK


		See http://hpc-journals.ecs.soton.ac.uk/Workshops/PEMCS/fall-97/


----------------------------------------------------------------------------------------------------

If you are interested in attending the Workshop you should register now and 
reserve accommodation as hotel rooms in Southampton during the workshop period
will be in short supply due to the "International Southampton Boat Show" which 
will also be taking place.

At present we have a preliminary reservation on rooms at the County Hotel where
the Workshop is being held. Without concrete delegate reservations we can only
hold onto there rooms for approximately another week.

Thereafter, accommodation at the Hotel, or around the city, may be more problematic
in getting and reserving. So, I encourage potential Workshop delegates to 
register ASAP.

Mark


-------------------------------------
Dr Mark Baker
University of Portsmouth, Hants, UK
Tel: +44 1705 844285	Fax: +44 1705 844006
E-mail: mab@sis.port.ac.uk
Date: 08/01/97 - Time: 17:17:52
URL http://www.sis.port.ac.uk/~mab/
-------------------------------------


From owner-parkbench-comm@CS.UTK.EDU Mon Aug 11 13:13:12 1997
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Date: Mon, 11 Aug 1997 13:02:12 -0400
To: alison.wall@rl.ac.uk, weber@scripps.edu, schauser@cs.ucsb.edu,
        dewombl@sandia.gov, edgorha@sandia.gov, rdskocy@sandia.gov,
        sales@pgroup.com, utpds@CS.UTK.EDU, parkbench-comm@CS.UTK.EDU,
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        atempt@gup.uni-linz.ac.at, rileyba@ornl.gov, bac@ccs.ornl.gov
From: "Michael F. McCarthy" <mmccarth@MIT.EDU>
Subject: For Sale: CM-5


   PLEASE FORWARD THIS NOTE TO ANYONE THAT YOU BELIEVE 
   MAY HAVE AN INTEREST IN PURCHASING THIS SYSTEM!
__________________________________________________________________________

Case #3971 -- FOR SALE - CM5 with 128 nodes and SDA --
__________________________________________________________________________

The MIT Lab for Computer Science offers for bid sale a Thinking Machines 
CM-5 Connection Machine (described below).  

Bids to purchase this system are requested from all interested parties,
(with a minimum expected Bid of $25,000).

All bids must be received at the MIT property office by 5:00 PM (EDT)
on Monday, 8/Sept/97.

The machine must be moved from MIT within 10 business days of  acceptance
of the bid. All expenses and arrangements for moving will be made by 
purchaser.

The system consists of:

1) 128 PN CM-5 w/ Vector Units, 256 Network addresses-Part 
          No.CM5-128V-32F
2) Scalable Disk Array with Twenty-four(24) 
          1.2 GB Drives-Part No.CM5-SA25F
3) Control Processor Interface-Part No. CM5-CPI
4) S-Bus to Diagnostics Network Interface-Part No. CM5-SDN
5) S-Bus Network Interface Board(5)-Part No. CM5-SNI

[N.B. On July 16 1997 power was turned off.The machine can be 
turned back on in its present location only until Friday, 22/AUG/97 
when wiring changes are planned in that machine room.]
 
"The Institute reserves the right to reject any or all offers.MIT makes no
warranty of any kind, express or implied, with respect to this equipment.
This includes fitness for a particular purpose. It is the responsibility of 
those making an offer to determine, before making an offer, that the
equipment meets any conditions required by those making that offer.Thank you."
__________________________________________________________________________

Submit bids for Case #3971  
                before Monday, 8/Sept/97, 5:00 PM (EDT) to: 
*****************************************************************
* Michael F. McCarthy       * Phone:  (617)253-2779             *
* MIT Property Office       * FAX:    (617)253-2444             *
* E19-429                   * E-Mail: mmccarth@MIT.EDU          * 
* 77 Massachusetts Ave.     *                                   *
* Cambridge, MA 02139       *                                   *
*****************************************************************
__________________________________________________________________________

SYSTEM HISTORY 

The Project SCOUT CM-5 is housed in M.I.T's Laboratory for Computer 
Science (L.C.S). The machine was acquired in 1993 as part of the the ARPA 
sponsored project SCOUT, and used to accomplish the stated aim of the 
project of "fermenting collaborations between users, builders and
networkers of massively parallel computers". The CM-5 computer, developed
and manufactured by Thinking Machines Corporation, evolved from earlier
T.M.C. computers (the CM-2 and the CM-200)with an architecture targeted 
toward teraflops performance for large, complex data intensive applications.

The MIT hardware consists of a total of 128 32MHz SPARC  microprocessors,
each with 4 proprietary floating point arithmetic units and 32Mb of local
memory attached to it. The system also includes a subsidiary 25Gb parallel 
file system for handling high volume parallel application I/O. 
 
The system was operated under full maintenance contract 
from May of 1993 until March 20 1997.

On July 16 1997 power was turned off. The machine can be turned back on
in its present location only until Friday, 22/AUG/97 when wiring changes 
are planned in that machine room.

The system was used primarily for research but a description of an 
instructional use made of the machine can be found at
     http://www-erl.mit.edu/eaps/seminar/iap95/cnh/CM5Intro.html

Web sites about other CM5 sites and general information include:
     http://www.math.uic.edu/~hanson/cmg.html
     http://www.acl.lanl.gov/UserInfo/cm5admin.html
     http://ec.msc.edu/CM5/

__________________________________________________________________________
FUTURE MAINTENANCE

People submitting bids may wish to discuss future maintenance issues
with a company that is a present maintainer of CM5 Equipment, 
Connection Machine Services. 
*****************************************************************
* Larry Stewart                * Phone:  (505) 820-1470         *
*                              * Cell:   (505) 690-7799         *
* Account Executive            * FAX:    (505) 820-0810         *
* Connection Machines Services * Home:   (505) 983-9670         *
* 1373 Camino Sin Salida       * Pager   (888) 712-4143         *
* Santa Fe, NM 87501           * E-Mail: stewart@ix.netcom.com  *
*****************************************************************
__________________________________________________________________________








Michael F. McCarthy
MIT Property Office
E19-429
77 Massachusetts Ave.
Cambridge, MA 02139
Ph   (617)253-2779
Fax  (617)253-2444


From owner-parkbench-comm@CS.UTK.EDU Mon Sep  1 05:44:50 1997
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Date: Mon,  1 Sep 97 10:19:23 +0000
From: Mark Baker  <mab@sis.port.ac.uk>
Subject: Final Announcement: Fall ParkBench Workshop
To: "Daniel A. Reed"  <reed@cs.uiuc.edu>,
        "J.C.T. Pool"  <jpool@cacr.caltech.edu>, a.j.grant@mcc.ac.uk,
        Antoine Hyaric  <Antoine.Hyaric@comlab.ox.ac.uk>,
        Ed Zaluska  <E.J.Zaluska@ecs.soton.ac.uk>,
        Fritz Ferstl  <ferstl@genias.de>, Hon W Yau  <hwyau@epcc.ed.ac.uk>,
        idh@soton.ac.uk, parkbench-comm@CS.UTK.EDU, parkbench-hpf@CS.UTK.EDU,
        Paul Messina  <messina@cacr.caltech.edu>,
        R.Rankin@Queens-Belfast.AC.UK, rjc@soton.ac.uk, topic@mcc.ac.uk,
        Wolfgang Genzsch  <getup@genias.de>
Cc: lec@ecs.soton.ac.uk
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Dear all,

This is the FINAL ANNOUNCEMENT:

If you would like to attend this workshop please let Lesley Courtney 
(lec@ecs.soton.ac.uk) know by Friday 5th September 1997 at 
the latest as we need to confirm numbers.

Workshop details can be found at

http://hpc-journals.ecs.soton.ac.uk/Workshops/PEMCS/fall-97/

Regards

Mark



-------------------------------------
Dr Mark Baker
University of Portsmouth, Hants, UK
Tel: +44 1705 844285	Fax: +44 1705 844006
E-mail: mab@sis.port.ac.uk
Date: 09/01/97 - Time: 10:19:23
URL http://www.sis.port.ac.uk/~mab/
-------------------------------------


From owner-parkbench-comm@CS.UTK.EDU Wed Sep  3 15:37:55 1997
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Date: Wed, 3 Sep 1997 16:31:07 +0100
To: parkbench-comm@CS.UTK.EDU
From: Roger Hockney <roger@minnow.demon.co.uk>
Subject: Prototype PICT release 1.0
MIME-Version: 1.0
X-Mailer: Turnpike Version 3.03a <kRL7V2isFfDmnKSZb08I5Tyfx$>

At their last meeting the Parkbench Committee recommended that an
interactive curve fitting tool be produced for the postprocessing and
parametrisation of Parkbench results using the latest Internet Web
technology. I have produced a prototype of such a tool as a Java applet
running on a Web page on the user's machine and called it PICT
(Parkbench Interactive Curve-fitting Tool). This is now ready for
evaluation and testing by the committee.

The tool provides the following features:

(1) Automatic plotting of Low-Level Parkbench output files from a URL
anywhere on the Web (At present limited to New COMMS1 and Raw data, but
easily extended to original COMMS1 and RINF1). This is useful for a
quick comparison of raw data.

(2) Automatic plotting of both 2 and 3-parameter curve-fits which are
produce by the benchmarks. Good for checking the quality of the fits.

(3) Allows manual rescaling of the graph range to suit the data, either
by typing in the required range values or by dragging out a range box
with the mouse.

(4) Allows the 2-parameter and 3-parameter performance curves to be
manually moved about the graph in order to fine tune the fits. The curve
follows the mouse and the RMS and MAX percentage errors are shown as the
curve moves. Alternatively parameter values can be typed in and the
Manual button pressed when the curve for these values will be plotted.

(5) The data file being plotted can be VIEWed and a HELP button provides
a description of the action of each button in a separate windows.

The PICT applet has been built on top of Leigh Brookshaw's 2D plotting
package the URL for which is given at the bottom of the HELP window. The
features under the RESTART button are in his original code, I have just
added the 2-PARA and 3-PARA features.

The applet was developed using JDK1.0 beta on a PC with a 1600x1200
display and works on the PC both locally and from my Web page with
appletview, MSIE 3.02 and Netscape 3.01. It has also been successfully
run on a Solaris Sun with NS3.01, but another Sun user has reported no
graphs and errors due to "wrong applet version". So please report your
experiences (both success and failure please) to me with all the
details.

To play with PICT turn your browser to:

     http://www.minnow.demon.co.uk/pict/source/pict1.html  or 
                                               pict1a.html 

pict1.html asks for 1000x732 pixels and suits PCs best (it's about the
minimum useful size).

pict1a.html asks for 1020x900 pixels and was necessary for the whole
applet to visible on the Sun.

For those wishing to look closer all the source is provided and should
be downloadable. Suggestions for improvement, corrections or
constructive criticism are solicited.

I have asked for an agenda item to be included for the Parkbench meeting
on 11 Sept in Southampton so that PICT can be discussed. I look forward
to seeing some of you there.
-- 
Roger Hockney.  Checkout my new Web page at URL   http://www.minnow.demon.co.uk
University of   and link to my new book: "The Science of Computer Benchmarking"
Westminster UK  suggestions welcome. Know any fish movies or suitable links?

From owner-parkbench-lowlevel@CS.UTK.EDU Wed Sep 10 06:29:15 1997
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To: parkbench-lowlevel@CS.UTK.EDU, parkbench-comm@CS.UTK.EDU,
        parkbench-hpf@CS.UTK.EDU
Subject: ParkBench Committee Meeting - tentative Agenda

Dear Colleague,

The ParkBench (Parallel Benchmark Working Group)
will meet in Southampton, U.K. on 
September 11th, 1997 as part of the ParkBench Workshop.

The Workshop site will be the County Hotel in Southampton.

  County Hotel
  Highfield Lane
  Southampton, U.K.
  Phone: +44-(0)1703-359955


Please send us your comments about the tentative agenda:


14:30  Finalize meeting agenda
       Minutes of last meeting (Erich Strohmaier)

14:45  Changes to Current release:
         - Low Level COMMS benchmarks (Vladimir Getov)
         - NAS Parallel Benchmarks (Subhash Saini)

15:15  New benchmarks:
         - HPF Low Level benchmarks (Mark Baker)


15:30  ParkBench Performance Analysis Tools:
         - ParkBench Result Templates (Vladimir Getov and Mark Papiani)
         - Visualization of Parallel Benchmark Results - new GBIS
           (Mark Papiani and Flavio Bergamaschi)
         - Interactive Web-page Curve-fitting of Parallel Performance
           Measurements (Roger Hockney)


16:15  Demonstrations:
         - Java Low-Level Benchmarks (Vladimir Getov)
         - BenchView: Java Tool for Visualization of Parallel Benchmark Results
           (Mark Papiani and Flavio Bergamaschi)
         - PICT: An Interactive Web-page Curve-fitting Tool (Roger Hockney)


16:45  Other activities:
         - "Electronic Benchmarking Journal" - status report (Mark Baker)


       Miscellaneous
       Date and venue for next meeting

17:00       Adjourn


Tony Hey
Vladimir Getov
Erich Strohmaier

From owner-parkbench-comm@CS.UTK.EDU Wed Sep 10 06:40:25 1997
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Date: Wed, 10 Sep 97 11:33:13 BST
Message-Id: <2458.9709101033@bill.ecs.soton.ac.uk>
To: parkbench-lowlevel@CS.UTK.EDU, parkbench-comm@CS.UTK.EDU,
        parkbench-hpf@CS.UTK.EDU
Subject: ParkBench Committee Meeting - tentative Agenda

Dear Colleague,

The ParkBench (Parallel Benchmark Working Group)
will meet in Southampton, U.K. on 
September 11th, 1997 as part of the ParkBench Workshop.

The Workshop site will be the County Hotel in Southampton.

  County Hotel
  Highfield Lane
  Southampton, U.K.
  Phone: +44-(0)1703-359955


Please send us your comments about the tentative agenda:


14:30  Finalize meeting agenda
       Minutes of last meeting (Erich Strohmaier)

14:45  Changes to Current release:
         - Low Level COMMS benchmarks (Vladimir Getov)
         - NAS Parallel Benchmarks (Subhash Saini)

15:15  New benchmarks:
         - HPF Low Level benchmarks (Mark Baker)


15:30  ParkBench Performance Analysis Tools:
         - ParkBench Result Templates (Vladimir Getov and Mark Papiani)
         - Visualization of Parallel Benchmark Results - new GBIS
           (Mark Papiani and Flavio Bergamaschi)
         - Interactive Web-page Curve-fitting of Parallel Performance
           Measurements (Roger Hockney)


16:15  Demonstrations:
         - Java Low-Level Benchmarks (Vladimir Getov)
         - BenchView: Java Tool for Visualization of Parallel Benchmark Results
           (Mark Papiani and Flavio Bergamaschi)
         - PICT: An Interactive Web-page Curve-fitting Tool (Roger Hockney)


16:45  Other activities:
         - "Electronic Benchmarking Journal" - status report (Mark Baker)


       Miscellaneous
       Date and venue for next meeting

17:00       Adjourn


Tony Hey
Vladimir Getov
Erich Strohmaier

From owner-parkbench-lowlevel@CS.UTK.EDU Thu Sep 18 18:27:19 1997
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Date: Thu, 18 Sep 1997 15:26:16 -0700 (PDT)
From: Mary E Zosel <zosel@k2.llnl.gov>
Message-Id: <199709182226.PAA07246@k2.llnl.gov>
To: parkbench-lowlevel@CS.UTK.EDU
Subject: any pthreads tests???

Does anyone know of any low-level performance tests for pthreads libraries???
I'm interested in both single processor performance of pthreads calls - 
and also multiprocessor (shared memory) calls ... to measure the overhead
of the calls.
  -mary zosel-   zosel@llnl.gov

From owner-parkbench-lowlevel@CS.UTK.EDU Sun Sep 21 09:13:20 1997
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Date: Sun, 21 Sep 97 13:32:56 +0000
From: Mark Baker  <mab@sis.port.ac.uk>
Subject: Re: any pthreads tests???
To: Mary E Zosel  <zosel@k2.llnl.gov>, parkbench-lowlevel@CS.UTK.EDU
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Mary,

This has been talked about as one of the activities that Parkbench
would be interested in persuing. But, so far we have not had the
time or man-power to follow up our interests.

Ron Sercely at HP/CTCX was particularly interested in this area. Also,
I know the people at Manchester University wrote a bunch of
Pthreads codes - some were benchmarks - for their KSR machine.

Hope this helps.

Regards

Mark


--- On Thu, 18 Sep 1997 15:26:16 -0700 (PDT)  Mary E Zosel <zosel@k2.llnl.gov> wrote:
> Does anyone know of any low-level performance tests for pthreads libraries???
> I'm interested in both single processor performance of pthreads calls - 
> and also multiprocessor (shared memory) calls ... to measure the overhead
> of the calls.
>   -mary zosel-   zosel@llnl.gov
> 

---------------End of Original Message-----------------

-------------------------------------
CSM, University of Portsmouth, Hants, UK
Tel: +44 1705 844285	Fax: +44 1705 844006
E-mail: mab@sis.port.ac.uk
Date: 09/21/97 - Time: 13:32:57
URL http://www.sis.port.ac.uk/~mab/
-------------------------------------


From owner-parkbench-comm@CS.UTK.EDU Wed Sep 24 06:04:19 1997
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	id AA29780; Wed, 24 Sep 97 10:47:01 BST
Date: Wed, 24 Sep 97 10:38:39 +0000
From: Mark Baker  <mab@sis.port.ac.uk>
Subject: PC timers
To: parkbench-comm@CS.UTK.EDU, parkbench-low-level@CS.UTK.EDU
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Can someone suggest the appropriate PC-based timer 
function (MS Visual C++ or Digital Visual Fortran)
to replace the usual gettimeofday call !?

Cheers

Mark

-------------------------------------
CSM, University of Portsmouth, Hants, UK
Tel: +44 1705 844285	Fax: +44 1705 844006
E-mail: mab@sis.port.ac.uk
Date: 09/24/97 - Time: 10:38:39
URL http://www.sis.port.ac.uk/~mab/
-------------------------------------


From owner-parkbench-comm@CS.UTK.EDU Thu Sep 25 10:11:01 1997
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Date: Thu, 25 Sep 97 14:11:59 +0000
From: Mark Baker  <mab@sis.port.ac.uk>
Subject: PC Time function
To: parkbench-comm@CS.UTK.EDU
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Thanks to all for timer info. I used the C function _ftime()
in the end because it had millisec resolution. Just had
to get a my head around using INTERFACE in F90 to include
the external C function.

I've inserted my version of the _ftime() timer below - I don't think
there are any obvious error in it :-)

I also implemented the dflib F90 function  CALL GETTIM(hour, min, sec, hund) -
this function passed tick2 testing but only has 1/100 sec resolution.

-------------------------------------------------------
double dwalltime00()
{

    struct _timeb timebuf;

    _ftime( &timebuf );

    return (double) timebuf.time + (double) timebuf.millitm / 1000.0;
}

double dwalltime00_()
{
	return dwalltime00();
}

double DWALLTIME00()
{
	return dwalltime00();
}
-------------------------------------------------------




Cheers

Mark




-------------------------------------
CSM, University of Portsmouth, Hants, UK
Tel: +44 1705 844285	Fax: +44 1705 844006
E-mail: mab@sis.port.ac.uk
Date: 09/25/97 - Time: 14:11:59
URL http://www.sis.port.ac.uk/~mab/
-------------------------------------


From owner-parkbench-comm@CS.UTK.EDU Tue Oct  7 06:35:04 1997
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Date: Tue,  7 Oct 97 10:43:49 +0000
From: Mark Baker  <mab@sis.port.ac.uk>
Subject: Workshop Papers
To: "Aad J. van der Steen"  <steen@fys.ruu.nl>, Charles Grassl  <cmg@cray.com>,
        Clemens Thole  <clemens-august.thole@gmd.de>,
        David Snelling  <snelling@fecit.co.uk>,
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Dear All,

I am now back in the office and have a small amount of time to follow
up the Parkbench Workshop that took place a few weeks ago.

I would firstly like to thanks everyone who attended - especially
all the speakers. Even though we did not attract hundreds of 
delegates to the workshop, I think the event was very successful 
- but I may be bias...

So, the plans are that in the first instance I will collect the slides
from all the speaker and package them up and put them on the PEMCS
Web site.

We also decided that we would encourage all the speaker to produce
short papers on their talks and put all the workshop paper together
to create a special issue the the PEMCES journal.

Can the speakers therefore send me their slides (I would prefer
powerpoint or word version if possible). I will harrass you further
about a short papers in the near future.

Thanks in advance for your help.

Regards

Mark



-------------------------------------
CSM, University of Portsmouth, Hants, UK
Tel: +44 1705 844285	Fax: +44 1705 844006
E-mail: mab@sis.port.ac.uk
Date: 10/07/97 - Time: 10:43:49
URL http://www.sis.port.ac.uk/~mab/
-------------------------------------


From owner-parkbench-comm@CS.UTK.EDU Sun Oct 12 09:55:57 1997
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Date: Sun, 12 Oct 97 14:35:10 +0000
From: Mark Baker  <mab@sis.port.ac.uk>
Subject: Equivalent to comms1
To: parkbench-comm@CS.UTK.EDU
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Can someone point me at the equivalant of comms1 written in
C - either MPI or sockets (or even PVM if its out there).

Cheers

Mark


-------------------------------------
Dr Mark Baker
CSM, University of Portsmouth, Hants, UK
Tel: +44 1705 844285	Fax: +44 1705 844006
E-mail: mab@sis.port.ac.uk
Date: 10/12/97 - Time: 14:35:10
URL http://www.sis.port.ac.uk/~mab/
-------------------------------------


From owner-parkbench-comm@CS.UTK.EDU Mon Oct 13 16:30:04 1997
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I would check out my mpbench on my web page....
It does PVM and MPI for now...

> Can someone point me at the equivalant of comms1 written in
> C - either MPI or sockets (or even PVM if its out there).
> 
> Cheers
> 
> Mark
> 
> 
> -------------------------------------
> Dr Mark Baker
> CSM, University of Portsmouth, Hants, UK
> Tel: +44 1705 844285	Fax: +44 1705 844006
> E-mail: mab@sis.port.ac.uk
> Date: 10/12/97 - Time: 14:35:10
> URL http://www.sis.port.ac.uk/~mab/
> -------------------------------------
> 

/%*\ Philip J. Mucci | GRA in CS under Dr. JJ Dongarra /*%\
\*%/ http://www.cs.utk.edu/~mucci  PVM/Active Messages \%*/ 

From owner-parkbench-comm@CS.UTK.EDU Mon Oct 20 10:37:14 1997
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