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\fBA Suite of BiPolar Benchmark Circuits for Operating Point Computation\fP
.sp 0.25i
.ce 2
Robert Melville San Chin Fang (AT&T Bell Labs)
Ljiljana Trajkovic Thomas Banwell (Bellcore)
.H 1 "Introduction"
This is a collection of bipolar circuits designed to exercise
operating point algorithms in circuit simulation programs.
The qualitative behavior of these circuits should be relatively
independent of device models.
In other words, the circuits will "do the same thing" over a large
range of transistor model parameters.
Of course, exact numerical values of node voltages and device currents
\fBwill\fP depend on model parameters, in some cases strongly so.
Therefore, in order to get a fair comparison, we describe certain
\fIqualitative\fP behavoir of each circuit which should be
reproduced in other benchmark studies.
For any particular implementation,
some experimentation with the circuits may be necessary in order
to reproduce the claimed qualitative behavior.
A reasonable experiment would be to attempt to reproduce the
solutions we claim for each example by using the
given node voltages as a starting point for Newton's
method.
.P
Solutions are reported in the form of \fItransistor icons\fP,
which show the operating state of each transistor in the
circuit at the DC operating point (or points).
The following figure sumarizes the icon notation.
Terminal currents are reckoned positive when flowing into
the device, thus \f(CWIe \fP is almost equal to the
negative of \f(CWIc \fP in normal operation of the transistor.
.PS
Q:[B:box ht 1.4 wid 1.4;
"\f(CWId\fP" at B.nw+(0.05,-0.3) ljust;
C:(12/14); E:(12/14);
line from (3/14) to (11/14);
line from (5/14) to B.c;
"\s-2\f(CWVc" ljust at B.ne+(-0.5,-0.06);
"Ve" ljust at B.se+(-0.5,0.05);
"Vb" ljust at B.w;
"Ic" ljust at B.ne+(-1.1,-0.15);
"Ie" ljust at B.se+(-1.1,0.1);
"Ib\s+2\fP" ljust at B.w+(0.05,-0.3);
"\s-2(eff-beta)\s+2" ljust at B.c+(0.1,0);
line from (4/14) to (3/14);
line from (1/14) to (3/14);
line from (4/14) to (5/14);
line from (1/14) to (5/14);
line -> from (4/14) to (3/14);
line from (1/14) to (3/14);
line -> from (4/14) to (5/14);
line from (1/14) to (5/14);
]
.PE
.FG "Transistor Icon"
Standard engineering suffixes are used for these currents:
.DS I
\f(CWm @10 sup -3@
u @10 sup -6@
n @10 sup -9@
p @10 sup -12@
f @10 sup -15@
a @10 sup -18@.
.DE
The \fIeffective beta\fP of the transistor is shown in the center, if the
base-emitter junction is not reverse biased.
This is simply the ratio of collector to base current for the particular
operating conditions of the transistor.
The collector-base junction is drawn "up" if @V sub cb ~>=~ -0.4@ volts
for an NPN transistor and if @V sub bc ~>=~ -0.4@ volts for a PNP
transistor.
Otherwise, the junction line is drawn "down" indicating that the
juction is forward biased.
The base emitter junction line is drawn down
(indicating normal forward bias) for @V sub be ~>=~ 0.5@
(NPN) and @V sub eb ~>=~ 0.5@ (PNP).
Current magnitudes smaller than @10 sup -18@ are indicated as
"~0~".
.P
Some of the circuits have multiple DC solutions.
In such a case, a solution may be \fBphysically unstable\fP
in the sense that if the circuit is placed in such an operating
state, it will immediately move to a neighboring stable DC solution
different from the unstable state.
The prototypical example of such behavior is a perfectly symmetric flip-flop.
The "middle" state\(emin which both transistors conduct
equal amounts of current\(emis unstable, and is only observed as a transitory
state inbetween one of the two symmetric stable states in which one transistor
is conducting and the other is off.
For certain circuits in our suite, consultation with a designer has identified
a DC solution as unstable,
even though it will be an exact zero of the operating point equations.
We take the position that an operating point algorithm should avoid such solutions,
or at least warn a user that an operating point may be electronically unstable.
.P
Node voltages are given to five decimal places.
Because many of the circuits have multiple solutions,
it is convenient to devise some sort of "signature"
for the different solutions.
Some of the performance data of section three is generated by a program
which exercises the circuit at fifty random values of a
parameter vector.
The exercising program uses the signature of a solution to
record a "hit" on that particular solution.
The signature is supposed to be like a "hash function" so that
different solutions will have different signatures with high
probability.
The scheme used here is to treat the @n@ node voltages
at solution\(emcall them @s sub 0 , ... , s sub n-1@\(emas
coefficients of an @(n-1)@-st degree polynomial evaluated at
the point 1.25.
Thus the signature is @s sub 0 + s sub 1 (1.25) + ... + s sub n-1 (1.25) sup n-1@
evaluated using Horner's rule.
.P
The quality of the claimed solution is indicated
by giving the two-norm the operating point equations at the reported
point.
.P
Our numerical implementation uses a transistor model adapted from the
excellent reference [1].
Specifically, we have implemented what Getreu calls "EM1" with the
reciprocity condition discussed on page 14.
Terminals resistances (@r sub c@, @r sub b@, and @r sub e@) are
not modeled (i.e., zero).
The thermal voltage @V sub T@ is set at 0.025 volts (room temperature)
and the saturation current @I sub s@ is @10 sup -16@ amperes.
The reverse current gain @alpha sub R@ is 0.5 for both NPN and PNP
transistors. The forward current gain @alpha sub F@ is 0.995 for NPN
devices and 0.98 for PNP devices.
Temperature dependence is not modeled.
Linear scaling of a transistor size is accomplished by multiplying
all terminal currents by the given scaling ratio.
The Early effect is not modeled (i.e., VA = infinite).
.P
The PN junctions were modeled with the classical diode
equation as discussed in [1] on page 12.
However, for forward bias greater than 0.95 volts,
a quadratic polynomial is substituted for the diode equation
as a form of current limiting.
This scheme is @C sup 2@.
Reverse breakdown is not modeled.
.P
All resistors are perfectly linear.
.P
Our operating point equations uses the
pure nodal formulation, and
our numerical experiments were done in double precision on
a SUN4 which uses the IEEE arithmetic standard.
Unless otherwise indicated, a claimed "solution"
means that the two-norm of the nodal equations was reduced to
@10 sup -14@ or smaller.
.H 1 "Performance Statistics"
The operating points reported for these circuits were obtained
with a variety of homotopy methods as described [2].
.P
These benchmark results were obtained using the routine \f(CWFIXPNS \fP
from the software package \f(CWHOMPACK \fP which is described in [3].
.P
When applied to a circuit with multiple solutions, the
homotopy methods described in [2] tend to converge
to one of the electronically stable solutions.
Modifications (e.g., deflation) are necessary
to find other solutions.
For this reason, the performance statistics reported below
concentrate on electronically stable solutions.
All times are reported in seconds.
Each circuit was solved using fifty different values of
a randomization parameter as described in [2].
The column "# Iterations" indicates the number
of times that a Jacobian matrix of the homotopy map
was computed.
Tests were run for two values of tracking tolerance,
as described in the \f(CWHOMPACK \fP documentation, 1E-6 and 1E-7.
The homotopy for the operating point computation includes a scaling
factor which controls the "degree of influence" of the random
starting point.
To exercise the computation from widely spaced starting points, this
parameter is set to 1 in the second column of runs.
However, a value of 1E-2 for the scale factor speeds up the computation
while still providing the benefit of the random element.
The scale factor is set to 1E-2 for the runs in the first column.
The "Test conditions" and "Notes" columns contain information peculiar to each
circuit with reference to the attached write-ups.
In the case of circuits with multiple solutions,
the "Notes" column contains a summary of the form
@alpha sub 1 "\fRS1\fP" + alpha sub 2 "\fRS2\fP"@ meaning that
solution 1 was found @alpha sub 1@ out of fifty times and solution
2 was found @alpha sub 2@ times.
The letter "F" indicates a failure to converge,
.P
The following results are for the "variable stimulus" homotopy
from [2].
.TS
box,center;
c s s s s s s s s
c c s s s s s c c
c c s s c s s c c
c c c c c c c c c
l | n n n | n n n | l | l.
Variable Stimulus Homotopy using \f(CWFIXPNS\fP
_
Circuit # Iterations Test conditions Notes
(1E-6,1E-2) (1E-7,1)
min avg max min avg max
_
Cascade 269 478 813 351 621 1299 50S1+0F
DcNine 147 219 335 163 290 463 21S7+19S3+3S2+7S9+0F
Brokaw 227 265 321 299 355 406 50S1+0F
Hybrid 272 351 468 346 435 604 5S1+45S3+0F
CmMode 155 407 632 310 494 787 edge of hyst. region E-6:48S1+2F; E-7:50S1+0F
CmMode 156 277 384 254 341 451 hyst. region E-6:46S1+2S3+2F; E-7:48S1+2S3+0F
.TE
.FG "Table 1\(emStatistics for the Variable Stimulus Homotopy from 50 Start Points"
.P
The above times are somewhat artificial and more expensive than necessary,
since the program
was forced to explore a large space of starting positions.
For the results in the following table, the scale factor for the random vector
was set to 1E-5, and a tracking tolerance of 1E-5 was used.
These numbers seem adequate for general purpose operating point computation.
.TS
box,center;
c s s s
c c c c
l | n | n | l.
Variable Stimulus Homotopy using \f(CWFIXPNS\fP
_
Circuit # Iterations Time(secs) Notes
_
Cascade 496 31.70
DcNine 127 7.60 S2 obtained
Brokaw 193 8.70 S3 obtained
Hybrid 184 7.25 S3 obtained
CmMode 195 7.75 hyst. region; S1 obtained
.TE
.FG "Table 2\(emStatistics for the Variable Stimulus Homotopy using Routine Tolerance"
.P
Reference [2] also proposes a hybrid scheme which uses a damped Newton
code to get the solution to a diode-only network which results from
setting the current gain of each transistor to zero,
then employs homotopy to bring the gains back to full value.
These tests were run only once for each circuit,
since the performance of the first phase is almost
independent of starting point.
Data are presented in the form "Phase1+Phase2" giving number
of iterations of the damped Newton code to find the
solution to the diode network, followed by the
number of homotopy iterations.
For these runs, the \f(CWFIXPQF \fP routine from
\f(CWHOMPACK \fP was used, which does more function
evaluations than \f(CWFIXPNF \fP, but fewer
evaluations of the Jacobian matrix.
.TS
box,center;
c s s
c c c
l | n l.
Variable Gain Homotopy
Circuit # Iterations Notes
_
Cascade 12+184
DcNine 9+23 S2 obtained
Brokaw 16+27 S3 obtained
Hybrid 23+16 S3 obtained
CmMode 16+46 edge of hyst. region
CmMode 18+24 hyst. region; S1 obtained
.TE
.FG "Table 3\(emStatistics for the Variable Gain Homotopy"
.H 1 "References"
.AL
.LI
Getreu, I., "Modeling the Bipolar Transistor",
Tektronix, Inc., Beaverton Oregon, 1976.
.LI
Melville, R.C., Lj. Trajkovic, S.C. Fang and L.T. Watson,
"Globally Convergent Homotopy Methods for the DC Operating
Point Problem", to appear in IEEE Transactions on
Computer Aided Design.
.LI
Watson, L.T. and A.P. Morgan, "Algorithm 652: HOMPACK A Suite of
Codes for Globally Convergent Homotopy Algorithms",
\fIACM TOMS\fP, Vol. 13, No. 3, Sept. 1987.
.LE